AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023

A.1.1. Source-Synchronous Interface Timing Constraints

For the FPGA device, SYSREF I/O timing constraint is a typical source-synchronous timing constraint case.

The following example explains the SYSREF I/O timing constraint script for the TimeQuest Timing Analyzer.

set clk_dev_period  xxx
create_clock -name virtual_clock -period $clk_dev_period
set clk_dev_delay  xxx
set sysref_delay  xxx
set max_output_skew xxx
set sysref_max_delay [expr $sysref_delay + $max_output_skew - $clk_dev_delay]
set sysref_min_delay [expr $sysref_delay - $max_output_skew - $clk_dev_delay]
set_input_delay -clock virtual_clock -max $sysref_max_delay [get_ports {sysref_in}]
set_input_delay -clock virtual_clock -min $sysref_min_delay [get_ports {sysref_in}]

The max_output_skew compensates some uncertainties in the system. The uncertainties include the jitter, PLL phase shift error, and duty cycle distortion.

The sysref_in is the SYSREF pin name in the FPGA design.

The following figure shows, the dotted line depicts the sysref_delay and clk_dev_delay if the SYSREF and clk_dev are aligned at the clock or SYSREF generator output. The PCB trace delay can be obtained from PCB simulation or estimated by the PCB trace length. If the buffer devices are used, also need to consider the buffer delay. However, if all the buffer channels have the same delay, they can be canceled out.

Figure 18.  SYSREF_delay and clk_dev_delay

If the SYSREF and clk_dev are not aligned at the clock/SYSREF generator output, the skew needs to be calculated into the sysref_delay or clk_dev_delay. For example, if SYSREF is 1 ns later than clk_dev at clock or SYSREF generator output, 1 ns should be added to sysref_delay.