2. Digital Phased Array Synchronization
The following figures show an example of the wavefront striking four antenna elements. In part (a) of the below figure Phased Array Beamforming, the wavefront arrives at the left most element first. After the ∆t time, it arrives at the second left element; ∆t time later, the next element, and the process continues. The receiving path has time delay modules. A combiner sums all channels’ signals, after the time delay modules.
The time difference of the wavefront striking the antenna elements is compensated when the time delay modules are configured with the delay values 3∆t, 2∆t, ∆t, and 0. The combiner output is a coherent stronger signal.
In part (b) of the below figure Phased Array Beamforming, for the signals from other angles, the time difference of the wavefront striking the antenna elements is different from the delays of the time delay modules. The combiner output is significantly reduced.
You can implement the time delay compensation and summation in the digital domain by using high-speed Analog to Digital Data Converter (ADC) to capture the antenna elements’ signals. The Phased Array (PA) here, is known as the Digital Phased Array (DPA).
The time-delay compensation and summation are precise, flexible, and configurable in the digital domain. The modern FPGA device has high-speed I/O and rich logic/memory resources. The FPGA device can connect to multiple antenna elements through the ADC and implement the DPA beamforming, as shown in the following figure.
The typical DPA system contains large number of elements. Using multiple data converters within such systems allows more precise digital beamforming, providing multiple beam patterns, and improved beam shape. Additionally, adaptive beamforming can supress interferences and jamming.
A single FPGA device does not have enough I/O and resources to interface all elements and dispose the data stream. Consequently, multiple FPGA devices are deployed in the DPA system. Each FPGA device connects to a subset of antenna elements. All the data converters and FPGA devices must be synchronized to provide coherent processing for all the DPA elements.
- Each FPGA device connects to 4 antenna elements.
- Each FPGA device receives data from antenna elements, compensates the time delay, and combines all channels’ data stream.
- For FPGA B, the combined data is sent to FPGA A, and is merged with the partial beamforming result of FPGA A to get the combined waveform of all 8 antenna elements.
- To monitor the data path, the hardware capture modules capture the data and sends it to the host for analysis.
The system is divided into four parts, shown as I, II, III, and IV. Each part has different characteristics and requirements for synchronization.
I: Analog Path
- Constant—the different delays of cables, connectors, Printed Circuit Board (PCB) traces, etc.
- Slowly changing delays—caused by temperature, aging, etc.
- Delay during power cycles or resets—ADC sampling point is randomly defined in power cycles.
To reduce the misalignment of part I, the delays of cables, connectors, and PCB traces in different channels must be exactly matched. The ADC clocks must be aligned to reduce the skew between different channels.
There are many methods to calibrate and align multiple ADC channels/devices with respect to the system, such as, using a common signal source to drive all ADC channels/devices, measuring the skews between channels/devices and doing compensation.
Refer to the respective ADC user guide to synchronize multiple ADC channels/devices.
II: Interconnections between ADCs and FPGAs
All other parts following part I are in the digital domain. Misalignment described in part II, III, and IV is the multiple of whole clock cycles.
Part II is the high-speed links between the ADCs and the FPGAs. Latency varies during power cycles because as data is transferred by the high-speed links, it goes across different clock domains and passes through FIFOs. Generally, different channels have different latencies.
For example, heterogeneous System-in-Package with ADC chiplets use interfaces like Advanced Interface Bus (AIB). This interface utilizes double data rate (DDR) wires and FIFOs to move data. Measurement and latency calibration is applied to force deterministic latency over the interface.
In contrast, the majority of discrete high-speed ADCs use JESD204B/C high-speed serial interface. JESD204B/C subclass 1 mode provides a method to measure and compensate for deterministic latency feature, which guarantees all the channels have the same deterministic latency in power cycles.
JESD204B/C Intel FPGA IP core is used to interface to discrete ADCs, and to connect multiple FPGAs. This inherently achieves deterministic latency in the interconnection.
III: Digital Logic in FPGA
The system typically has one root source of clocks. This is to guarantee the FPGA devices are driven by coherent clocks. However, inside each FPGA, this clock passes different delays due to design variations, or generally process, voltage, and temperature (PVT) variation. When there is any communication between multiple FPGAs, the inter-FPGA signals must be synchronized.
Clock domain crossing also causes uncertainty in latency between the FPGA devices. Uncertainty in latency is also observed when two FPGA, devices designs are not identical. For example, the beamformer output of FPGA B is sent to FPGA A. The design must ensure that data from FPGA A and FPGA B are synchronized to get a coherently combined result of all 8 elements. Refer to FPGA Design Synchronization and Data Exchange between FPGA Devices for detailed description.
IV: Event Trigger Synchronization
The trigger signals of the events must be synchronized to guarantee a complete system synchronization.
For example, the trigger signals must be synchronized to ensure the hardware capture modules capture the data synchronously in both FPGA A and FPGA B.