AN 967: Multiple Device Synchronization in Digital Phased Array System

ID 734485
Date 12/15/2023
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3.2. Clock/SYSREF Scheme

Clocking circuits must supply adequate support to enable consistent and stable ADC alignment, to support all the DPA elements alignment.

The following figure Clocks and JESD204B/C Interface in DPA System Synchronization shows the use of the JESD204B/C interface to interconnect FPGA devices to support synchronized data exchange. The figure also shows the simplified connection diagram of the clocking circuitry and the JESD204B/C interface.


  • Two ADCs are connected to an FPGA device
  • Two FPGA devices in the system
Figure 4. Clocks and JESD204B/C Interface in DPA System Synchronization

All the clocks must originate from the same source to ensure coherent operation of all data converters and signal processing in the FPGA.

Some ADC devices provide separate clocks— the reference clock (clk_ref) for data converting engine to define sampling point and the device clock (clk_dev) for the digital part and interface.

The JESD204B/C interface is typically used for the connections between data converters and FPGAs. With JESD204B/C Intel FPGA IP cores, it can also be used to connect FPGA devices for data exchange.

SYSREF signals provide support for the JESD204B/C subclass 1 deterministic latency feature. SYSREF is synchronized and sampled by clk_dev. Generally, the same clock device generates clk_dev and SYSREF to guarantee the synchronization and phase relationship.

SYSREF signal can be triggered by the SYSREF_req signal. All the SYSREF_req signals are ‘OR’ together, so any FPGA device can assert SYSREF_req to request SYSREF.

If the system needs more clk_ref, clk_dev, and SYSREF signals, you may use the buffer devices for duplication.