JESD204C Intel® FPGA IP User Guide

ID 683108
Date 10/22/2021
Public
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Document Table of Contents

1. About the JESD204C Intel FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.3
IP Version 1.1.0

This user guide provides the features, architecture description, steps to instantiate, and guidelines to design the JESD204C Intel® FPGA IP using Intel® Stratix® 10 and Intel® Agilex™ devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the JESD protocol.
Table 1.  Related Documents
Reference Description
JESD204C Intel® Agilex™ Design Example User Guide Provides information about how to instantiate JESD204C design examples using Intel® Agilex™ devices.
JESD204C Intel® Stratix® 10 Design Example User Guide Provides information about how to instantiate JESD204C design examples using Intel® Stratix® 10 devices.
JESD204B Intel® FPGA IP User Guide Provides information about the JESD204B Intel® FPGA IP.
Intel® Agilex™ Device Data Sheet

This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.

Intel® Stratix® 10 Device Data Sheet Provides information about the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Stratix® 10 devices
E-Tile Transceiver PHY User Guide Provides information about the E-tile Transceiver PHY.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
LEMC Local Extended Multiblock Clock
FC Frame clock rate
ADC Analog to Digital Converter
DAC Digital to Analog Converter
DSP Digital Signal Processor
TX Transmitter
RX Receiver
DLL Data link layer
CSR Control and status register
CRU Clock and Reset Unit
ISR Interrupt Service Routine
FIFO First-In-First-Out
SERDES Serializer Deserializer
ECC Error Correcting Code
FEC Forward Error Correction
SERR Single Error Detection (in ECC, correctable)
DERR Double Error Detection (in ECC, fatal)
PRBS Pseudorandom binary sequence
MAC Media Access Controller. MAC includes protocol sublayer, transport layer, and data link layer.
PHY Physical Layer. PHY typically includes the physical layer, SERDES, drivers, receivers and CDR.
PCS Physical Coding Sub-layer
PMA Physical Medium Attachment
RBD RX Buffer Delay
UI Unit Interval = duration of serial bit
RBD count RX Buffer Delay latest lane arrival
RBD offset RX Buffer Delay release opportunity
SH Sync header
TL Transport layer
Table 3.  Glossary List
Term Description
Converter Device ADC or DAC converter
Logic Device FPGA or ASIC
Octet A group of 8 bits, serving as input to 64/66 encoder and output from the decoder
Nibble A set of 4 bits which is the base working unit of JESD204C specifications
Block A 66-bit symbol generated by the 64/66 encoding scheme
Line Rate

Effective data rate of serial link

Lane Line Rate = (Mx Sx N’x 66/64 x FC) / L

Link Clock

The associated parallel data will be 128 bit/132 bit instead of 64 bit/66 bit.

Link Clock = Lane Line Rate/132.

Frame A set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal.
Frame Clock A system clock which runs at the frame's rate, that must be 1x, 2x, or 4x link clock.
Samples per frame clock

Samples per clock, the total samples in frame clock for the converter device.

LEMC Internal clock used to align the boundary of the extended multiblocks between lanes and into the external references (SYSREF or Subclass 1).
Subclass 0 No support for deterministic latency. Data should be immediately released upon lane to lane deskew on receiver.
Subclass 1 Deterministic latency using SYSREF.
Multipoint Link Inter-device links with 2 or more converter devices.
64B/66B Encoding Line code that maps 64-bit data to 66 bits to form a block. The base level data structure is a block that starts with 2-bit sync header.
Table 4.  Symbols
Term Description
L Number of lanes per converter device
M Number of converters per device
F Number of octets per frame on a single lane
S Number of samples transmitted per single converter per frame cycle
N Converter resolution
N’ Total number of bits per sample in the user data format
CS Number of control bits per conversion sample
CF Number of control words per frame clock period per link
HD High Density user data format
E Number of multiblocks in an extended multiblock

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