JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 2/10/2023
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the JESD204C Intel® FPGA IP User Guide

3.1. Clocks

The JESD204C IP runs on link clock (link layer) and frame clock (transport layer). The transceiver runs in the link clock domain and the serial clock domain.

Table 13.   JESD204C IP Clocks
Clock Signal Formula Description

TX/RX device clock

j204c_pll_refclk

PLL selection The device clock is the PLL reference clock to the transceiver PLL.

TX/RX link clock

j204c_txlink_clk

j204c_rxlink_clk

Line rate/132 The timing reference for the JESD204C IP. The link clock is line rate divided by 132 because the link clock operates in a 132-bit data bus domain architecture after 64B/66B encoding.

TX/RX frame clock

j204c_txframe_clk

j204c_rxframe_clk

(Link clock frequency*FCLK_MULP) MHz The frame clock as per the JESD204C specification. The frame clock is always 1x, 2x, or 4x of the link clock.

.

TX/RX Avalon-MM (AVMM) clock

j204c_tx_avs_clk

j204c_rx_avs_clk

— The configuration clock for the JESD204C IP control and status registers through the Avalon-MM interface. This clock is asynchronous to all the other clocks. The frequency range of this clock is 75–125 MHz.

TX/RX PHY clock

j204c_txphy_clk

j204c_rxphy_clk

Line rate/64

The PHY clock internally generated from the transceiver parallel clock for the TX path or the recovered clock generated from the CDR for the RX path.

Transceiver reconfig clock

j204c_reconfig_clk

— The transceiver reconfiguration clock. The frequency range of this clock is 100–162 MHz.

Section Content
Device Clock
Frame Clock and Link Clock

Level Two Title