JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 2/10/2023
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the JESD204C Intel® FPGA IP User Guide

7. Interface Signals

The JESD204C Intel® FPGA IP uses the signals from the following interfaces.

Table 21.   JESD204C Intel® FPGA IP Interfaces
Interface Description
JESD204C MAC to and from the PHY interface
  • The IP allows you to generate PHY only, MAC only, or MAC and PHY configurations.
  • The PHY only generation is to provide a clean interface between the MAC and the PHY, where these signals are useful for debugging link and PHY issues.
  • The PHY mode has less number of PLLs in the transceiver, because the transmit channels will be bonded when generated together thus requiring less PLLs. Channel bonding also reduces the lane to lane skew on the transmit path.
Avalon® memory-mapped interface
  • The IP uses the Avalon® memory-mapped interface for reading and writing on the JESD204C IP slave component in a memory-mapped system.
  • The Avalon® memory-mapped slave interface allows upstream devices to access internal control and status registers.
  • The Avalon® memory-mapped slave is referred to as Management interface.
  • The Avalon® memory-mapped slave interface is designed as an asynchronous domain to the JESD204C Link clock and Frame clock domains.
  • If you want to keep the Avalon® memory-mapped slave interface as a synchronous domain to the JESD204C Link clock domain, you may do so provided that the domain is within the minimum and maximum frequency specified for j204_tx_avs_clk or j204_rx_avs_clk.
Avalon® streaming interface
  • The IP uses the following types of Avalon® streaming interface signals:
    • Avalon® streaming data interface, which operates in txframe_clk and rxframe_clk domains.
    • Avalon® streaming control sample interface, which operates in txframe_clk and rxframe_clk domains.
    • Avalon® streaming command interface, which operates in txlink_clk and rxlink_clk domains.
Note: You should terminate any unused signals.

Section Content
Transmitter Signals
Receiver Signals

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