JESD204C Intel® FPGA IP User Guide

ID 683108
Date 2/10/2023
Public

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Document Table of Contents

3. Functional Description

The JESD204C IP consists of scrambler and descrambler, transport layer, data link layer and physical layer.

The transport layer maps and packetizes the data samples into JESD204C frame data format. The transport layer operates in the parameters of M, N, S, CS and CF and maps into the parameters of F octets and L lanes. The transport layer is part of the JESD204C IP.

This IP supports line rate up to 28.9 Gbps per lane, and uses device clock which in turns generates the desired internal clocks for the transceivers and core logic. The frame clock does not need to be a physical input to the FPGA based on the JESD204C Specification.

To support multidevice synchronization, JESD204C IP uses Local Extended Multiblock Clock (LEMC) as a common timing reference. The IP generates the LEMC counter and uses SYSREF to align and reset the LEMC counter.

The IP supports Subclass 0 and Subclass 1. With Subclass 1, the IP can use the SYSREF signal and Device clock routed to achieve deterministic latency between the logic and converter devices.