1. About the F-Tile JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
|Intel® Quartus® Prime Design Suite 22.1
|IP Version 1.1.0
This user guide provides the features, usage guidelines, and detailed description about the design examples for the F-Tile JESD204B Intel® FPGA IP using Intel® Agilex™ devices.
This document is intended for:
- Design architect to make IP selection during system level design planning phase
- Hardware designers when integrating the IP into their system level design
- Validation engineers during system level simulation and hardware validation phase
|F-Tile JESD204B Intel® FPGA IP User Guide
|This document provides information about the F-Tile JESD204B Intel® FPGA IP.
|F-Tile JESD204B Intel® FPGA IP Release Notes
|This document provides release information for the F-Tile JESD204B Intel® FPGA IP.
|Intel® Agilex™ Device Data Sheet
This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.
Acronyms and Glossary
|Local Multiframe Clock
|Frame clock rate
|Analog to Digital Converter
|Digital to Analog Converter
|Digital Signal Processor
|Data link layer
|Control and status register
|Clock and Reset Unit
|Interrupt Service Routine
|Error Correcting Code
|Single Error Detection (in ECC, correctable)
|Double Error Detection (in ECC, fatal)
|Pseudorandom binary sequence
|Media Access Controller. MAC includes protocol sublayer, transport layer, and data link layer.
|Physical Layer. PHY typically includes the physical layer, SERDES, drivers, receivers and CDR.
|Physical Coding Sub-layer
|Physical Medium Attachment
|RX Buffer Delay
|Unit Interval = duration of serial bit
|RX Buffer Delay latest lane arrival
|RX Buffer Delay release opportunity
|ADC or DAC converter
|FPGA or ASIC
|A group of 8 bits, serving as input to 8B/10B encoder and output from the decoder
Effective data rate per lane for serial link
Data Rate = Sampling rate per converter x M x N' x (10/8)/L
Note: Sampling rate in Msps (Mega samples per second); Data rate in Mbps (Megabits per second)
The associated parallel data bus is 40 bits wide.
Link Clock = Data Rate/40.
|A set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal.
|A system clock which runs at the frame's rate.
|Samples per frame clock
Samples per clock, the total samples in frame clock for the converter device.
Local multiframe clock is counter generated from the link clock and depends on the F and K parameters.
LMFC Period = (FxK/4) x Link Clock Period; the value of FxK must be divisible by 4.
|No support for deterministic latency. Data should be immediately released upon lane to lane deskew on receiver.
|Deterministic latency using SYSREF.
|Inter-device links with 2 or more converter devices.
|Number of lanes per converter device
|Number of converters per device
|Number of octets per frame on a single lane
|Number of samples transmitted per single converter per frame cycle
|Total number of bits per sample in user data format
|Number of control bits per conversion sample
|Number of control words per frame clock period per link
|High Density user data format