F-Tile JESD204B Intel® FPGA IP Design Example User Guide
ID
729497
Date
7/15/2022
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1. About the F-Tile JESD204B Intel® Agilex™ FPGA IP Design Example User Guide
2. F-Tile JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204B Design Example
4. Document Revision History for the F-Tile JESD204B Intel® FPGA IP Design Example User Guide
3. Detailed Description for the F-Tile JESD204B Design Example
The F-Tile JESD204B design example demonstrates the functionality of data streaming using loopback mode.
You can specify the parameters settings of your choice and generate the design example.
The design example is available only in duplex mode for both Base and PHY variant.