AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Unsynchronized ADC- Intel® Stratix® 10 Multi-Link

For unsynchronized RX IP cores within the Intel® Stratix® 10 FPGA, each IP core operates independently. Because there is no alignment needed between the IP cores, the dev_lane_aligned port is connected to the alldev_lane_aligned port of each IP core. The IP cores can be out of reset at different time to complete the link initialization sequence. Each IP core is put into the different JESD204B subsystems and reset by the reset sequencers independently.

The combined SYNC_N signal is not necessary for unsynchronized ADC interfaces. SYNC_N signal from each IP core is connected to corresponding the ADC separately. This connection applies to Subclass 0, 1 and 2 ADC-FPGA pair.

For Subclass 1, the SYSREF pulse is the timing reference for the entire JESD204B subsystem. The rise of SYNC_N signals and the transition from code group synchronization (CGS) to initial lane alignment sequence (ILAS) is controlled by SYSREF. It is important to phase-aligned the SYSREF pulses to the FPGA and ADC pair within the same subsystem only. Phase alignment between subsystem is not required.

Figure 9. Multi-Link Use Case of Unsynchronized ADCs and FPGA with Non-combined SYNC_N
Figure 10. Clock and Reset Scheme of The Unsynchronized Multi-link