AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis

The RX Platform Designer system for simulation uses Avalon-MM BFM to perform write/read transactions to access the IP core CSR. For implementation on hardware, the Avalon-MM BFM is replaced with the JTAG to Avalon Master Bridge component.
  1. In the working folder, open the Intel® Quartus® Prime project, altera_jesd204_ed_RX.qpf.
  2. Open the top-level Platform Designer system, altera_jesd204_ed_qsys_RX.qsys, in Platform Designer.
  3. Insert the JTAG to Avalon Master Bridge component and you can rename the component as JTAG_AVMM_Bridge.
  4. Connect the JTAG to Avalon Master Bridge component ports as shown in the following table.
    Ports for Duplicated IP Core Connection
    clk mgmt_clk.clk
    clk_reset JTAG_reset.out_reset


    altera_jesd204_subsystem_RX1.mm_bridge_s0 (unsynchronized multi-link)




  5. Export the master_reset port of the JTAG to Avalon Master Bridge component.
  6. Export the in_reset port of the JTAG_reset component.
  7. Disable or delete the Altera Avalon-MM Master BFM component, mm_master_bfm_0.
  8. Click Generate HDL.
  9. Click Generate and Yes to save and generate the design files for compilation.
  10. Click Finish to save your Platform Designer settings and exit the Platform Designer window.
  11. Remove the JTAG to Avalon Master Bridge component, ip/altera_jesd204_ed_qsys_RX/altera_jesd204_ed_qsys_RX_JTAG_AVMM_Bridge.ip from the to Intel® Quartus® Prime setting files.
    This IP file is originated from the ed_synth folder. In the current project, JTAG to Avalon Master Bridge has the altera_jesd204_ed_qsys_RX_master_0.ip file.

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