Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis
- In the working folder, open the Intel® Quartus® Prime project, altera_jesd204_ed_RX.qpf.
- Open the top-level Platform Designer system, altera_jesd204_ed_qsys_RX.qsys, in Platform Designer.
- Insert the JTAG to Avalon Master Bridge component and you can rename the component as JTAG_AVMM_Bridge.
- Connect the JTAG to Avalon Master Bridge component ports as shown in the following table.
Ports for Duplicated IP Core Connection clk mgmt_clk.clk clk_reset JTAG_reset.out_reset master
altera_jesd204_subsystem_RX1.mm_bridge_s0 (unsynchronized multi-link)
- Export the master_reset port of the JTAG to Avalon Master Bridge component.
- Export the in_reset port of the JTAG_reset component.
- Disable or delete the Altera Avalon-MM Master BFM component, mm_master_bfm_0.
- Click Generate HDL.
- Click Generate and Yes to save and generate the design files for compilation.
- Click Finish to save your Platform Designer settings and exit the Platform Designer window.
- Remove the JTAG to Avalon Master Bridge component, ip/altera_jesd204_ed_qsys_RX/altera_jesd204_ed_qsys_RX_JTAG_AVMM_Bridge.ip from the to Intel® Quartus® Prime setting files.
This IP file is originated from the ed_synth folder. In the current project, JTAG to Avalon Master Bridge has the altera_jesd204_ed_qsys_RX_master_0.ip file.
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