AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
Public
Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis

The RX Platform Designer system for simulation uses Avalon-MM BFM to perform write/read transactions to access the IP core CSR. For implementation on hardware, the Avalon-MM BFM is replaced with the JTAG to Avalon Master Bridge component.
  1. In the working folder, open the Intel® Quartus® Prime project, altera_jesd204_ed_RX.qpf.
  2. Open the top-level Platform Designer system, altera_jesd204_ed_qsys_RX.qsys, in Platform Designer.
  3. Insert the JTAG to Avalon Master Bridge component and you can rename the component as JTAG_AVMM_Bridge.
  4. Connect the JTAG to Avalon Master Bridge component ports as shown in the following table.
    Ports for Duplicated IP Core Connection
    clk mgmt_clk.clk
    clk_reset JTAG_reset.out_reset
    master

    altera_jesd204_subsystem_RX.mm_bridge_s0

    altera_jesd204_subsystem_RX1.mm_bridge_s0 (unsynchronized multi-link)

    pio_control.s1

    pio_status.s1

    spi_0.spi_control_port

  5. Export the master_reset port of the JTAG to Avalon Master Bridge component.
  6. Export the in_reset port of the JTAG_reset component.
  7. Disable or delete the Altera Avalon-MM Master BFM component, mm_master_bfm_0.
  8. Click Generate HDL.
  9. Click Generate and Yes to save and generate the design files for compilation.
  10. Click Finish to save your Platform Designer settings and exit the Platform Designer window.
  11. Remove the JTAG to Avalon Master Bridge component, ip/altera_jesd204_ed_qsys_RX/altera_jesd204_ed_qsys_RX_JTAG_AVMM_Bridge.ip from the to Intel® Quartus® Prime setting files.
    This IP file is originated from the ed_synth folder. In the current project, JTAG to Avalon Master Bridge has the altera_jesd204_ed_qsys_RX_master_0.ip file.
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