AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
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Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link

  1. Open the top-level system, altera_jesd204_ed_qsys_RX.qsys, in Platform Designer.
  2. In the System Contents tab, right-click the altera_jesd204_subsystem_RX instance and select Drill into Subsystem. This opens the altera_jesd204_subsystem_RX Platform Designer subsystem.
  3. Right-click the altera_jesd204_RX component and select Duplicate.
    This duplicates the JESD204B IP core. You can rename the duplicated IP core as altera_jesd204_RX1.
    Note: Select No if the Platform Designer prompts Do you want to also duplicate the IP Variant file on the disk?. This is because the duplicated JESD204B IP core has the same parameters as the original JESD204B IP core.
  4. Connect the duplicated IP port as shown in the following table.
    Ports for Duplicated IP Core Connection
    jesd204_rx_avs mm_bridge.m0
    jesd204_rx_avs_clk mgmt_clk.clk
    jesd204_rx_avs_rst_n reset_seq.reset_out5
    rxlink_clk link_clk.clk
    pll_ref_clk

    refclk_xcvr.clk 4

    reconfig_clk mgmt_clk.clk 5
    reconfig_reset mgmt_clk.clk_reset 5
    reconfig_avmm mm_bridge.m0 5
  5. Export the rest of the ports to the top-level Platform Designer system by clicking the Double-click to export in the Export column of the System Contents tab.
  6. At the altera_jesd204_RX component, disconnect the connections at the following ports. Export them to the top-level Platform Designer system.
    • alldev_lane_aligned
    • dev_lane_aligned
    • rx_analogreset
    • rx_analogreset_stat
    • rx_digitalreset
    • rx_digitalreset_stat
    • rx_cal_busy
    • rx_islockedtodata
  7. Change the number of transceiver channels in the Transceiver PHY reset controller to the total number of transceiver channels of all the JESD204B IP cores in the altera_jesd204_subsystem_RX Platform Designer subsystem.
  8. Exports the following ports from the Transceiver PHY reset controller:
    • rx_analogreset
    • rx_analogreset_stat
    • rx_digitalreset
    • rx_digitalreset_stat
    • rx_cal_busy
    • rx_is_lockedtodata
  9. At the Address Map, adjust the starting address of altera_jesd204_RX1 interface so that there is no conflict with other components. For example, you can set the starting address of altera_jesd204_RX1 IP core to 0x000d_0400 as shown in the following table.
    Table 6.  Synchronized ADC-FPGA Multi-Link Address Map for System Console Control Path (Dynamic reconfiguration for the PHY is disabled)
      mm_bridge.m0
    altera_jesd204_RX.jesd204_rx_avs 0x000d_0000 – 0x000d_03ff
    altera_jesd204_RX1.jesd204_rx_avs 0x000d_0400 – 0x000d_07ff
    Table 7.  Synchronized ADC-FPGA Multi-Link Address Map for System Console Control Path (Dynamic reconfiguration for the PHY is enabled)
      mm_bridge.m0
    altera_jesd204_RX.jesd204_rx_avs 0x000d_0000 – 0x000d_03ff
    altera_jesd204_RX.reconfig_avmm 0x0000_0000 – 0x0000_1fff 6
    altera_jesd204_RX1.jesd204_rx_avs 0x000d_0400 – 0x000d_07ff
    altera_jesd204_RX1.reconfig_avmm 0x0000_2000 – 0x0000_3fff 6
  10. Repeat step 3 until step 9 for subsequent links in your design.
  11. Go up to the top-level Platform Designer system.
  12. Export the rest of unconnected ports of altera_jesd204_subsystem_RX instance.
  13. Click Generate HDL to generate the design files needed for Intel® Quartus® Prime compilation.
    1. Click Generate and Yes to save and generate the design files.
  14. After the HDL generation is completed, select Generate from the menu. Select Show Instantiation Template… and click Copy.
  15. Paste the instantiation template of altera_jesd204_ed_qsys_RX Platform Designer to a text editor.
    You must update the instantiated Platform Designer ports at the top-level HDL.
  16. After the HDL generation is completed, click Finish to save your Platform Designer settings and exit the Platform Designer window.
4 You cannot share the same transceiver reference clock pin for transceiver channels at different transceiver tiles. For this case, you should instantiate multiple refclk_xcvr clock sources in Platform Designer and connect them to the transceiver reference clock pins at different transceiver tiles.
5 Connection is applicable only if you turn on the Enable Transceiver Dynamic Reconfiguration option.
6 The address span of the PHY reconfiguration interface depends on the number of transceiver channels.
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