AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis

There are minor differences between the top-level HDL for Simulation and Synthesis. Perform the following steps to migrate the top-level HDL.
  1. Add the jtag_avmm_rst wire.
    wire   jtag_avmm_rst;
  2. Add jtag_avmm_rst signal to the mgmt_rst_in_n signal assignment statement. Replace global_rst_n signal with db_global_rst_n signal:
    assign mgmt_rst_in_n = db_global_rst_n & ~hw_rst & ~jtag_avmm_rst;
  3. Add JTAG to Avalon-MM Master Bridge reset to the Platform Designer system instantiation.
    .jtag_avmm_bridge_master_reset_reset (jtag_avmm_rst),
    .jtag_reset_in_reset_reset_n (1’b1),
  4. Start Analysis and Synthesis. You can use RTL Viewer to confirm the connections made in the previous steps are correct.
After completing these steps, proceed to perform tasks described in the Design Synthesis Guidelines.