AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link

  1. Open the top-level system, altera_jesd204_ed_qsys_RX.qsys, in Platform Designer.
    1. The RX Platform Designer file is located at ed_sim/testbench/models/ folder.
    2. To open the .qsys file in Platform Designer, you must have an associated Intel® Quartus® Prime project. Copy the altera_jesd204_ed_RX.qpf and altera_jesd204_ed_RX.qsf files from the ed_synth folder into ed_sim/testbench/models folder.
    3. Select the altera_jesd204_ed_RX.qpf and click Open.
    4. The IP Synchronization Result window opens and click OK to proceed.
  2. Each JESD204B link is represented by a single altera_jesd204_subsystem_RX instantiation. To implement multi-link in Platform Designer, right click the altera_jesd204_subsystem_RX instantiations and select Duplicate.
    You can rename the duplicated module as altera_jesd204_subystem_RX1.
  3. Connect the altera_jesd204_subsystem_RX1 ports as shown in the following table.
    Ports for altera_jesd204_subsystem_RX1 Module Connection
    refclk_xcvr refclk_xcvr.clk 7
    do_not_connect_reset_0 mgmt_clk.clk_reset
    do_not_connect_reset_1 mgmt_clk.clk_reset
    do_not_connect_reset_2 mgmt_clk.clk_reset
    frame_clk frame_clk.clk
    mm_bridge_s0 mm_master_bfm_0.m0
    link_clk link_clk.clk
    mgmt_clk mgmt_clk.clk
    mgmt_reset reset_controller_0.reset_out
    reset_seq_reset_in0 reset_controller_0.reset_out
  4. Leave reset_seq_pll_reset port of the altera_jesd204_subsystem_RX1 module unconnected.
  5. Export the rest of the ports to the top-level Platform Designer system by clicking on the Double-click to export in the Export column of the System Contents tab.
  6. Assign the address map of the altera_jesd204_subsystem_RX1 module in the Address Map tab. Assign the address map according to the following table.
    Table 8.  Unsynchronized ADC-FPGA Multi-Link Address Map for System Console Control Path Applicable when the dynamic reconfiguration for the PHY is either disabled or enabled.


    altera_jesd204_subsystem_RX.mm_bridge_s0 0x0000_0000 - 0x000f_ffff
    altera_jesd204_subsystem_RX1.mm_bridge_s0 0x0010_0000 - 0x001f_ffff
  7. Repeat steps 2 until step 6 for subsequent links in your design.
  8. Click Generate HDL to generate the design files needed for Intel® Quartus® Prime compilation.
    1. Ensure you select the HDL language of your choice in the Simulation section of the Generation windows to generate the simulation models.
    2. Click Generate and Yes to save and generate the design files needed for simulation.
  9. After the HDL generation is completed, select Generate from the menu. Select Show Instantiation Template… and click Copy.
  10. Paste the instantiation template of altera_jesd204_ed_qsys_RX Platform Designer to a text editor.
    You must update the instantiated Platform Designer ports at the top-level HDL.
  11. After the HDL generation is completed, click Finish to save your Platform Designer settings and exit the Platform Designer window.
7 You cannot share the same transceiver reference clock pin for transceiver channels at different transceiver tiles. For this case, you should instantiate multiple refclk_xcvr clock sources in Platform Designer and connect them to the transceiver reference clock pins at different transceiver tiles.