Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link
- Open the top-level HDL file (altera_jesd204_ed_TX.sv) in a text editor.
- Modify the LINK system parameter to reflect the number of links in your design.
- Insert the newly exported ports from the Platform Designer at the Platform Designer instantiation.
- Follow these steps to make the connections for the Platform Designer ports:
- For TX link reset, distribute the tx_link_rst_n wire from the reset sequencer in Platform Designer to IP cores and transport layers of the second and subsequent links. One way to achieve this is to hard code the index in tx_link_rst_n[i] wire in the transport layer instantiations generation loop with tx_link_rst_n.
- For TX frame reset, distribute the tx_frame_rst_n wire from the reset sequencer in Platform Designer to the transport layers and pattern checkers of the second and subsequent links. One way to achieve this is to hard code the index in tx_frame_rst_n[i] wire in the transport layer and pattern generator instantiations generation loop with tx_frame_rst_n.
- Create the following wires to handle PHY resets. Example is shown in Verilog HDL:
- wire [LINK*L-1:0] tx_analogreset;
- wire [LINK*L-1:0] tx_analogreset_stat;
- wire [LINK*L-1:0] tx_digitalreset;
- wire [LINK*L-1:0] tx_digitalreset_stat;
- wire [LINK*L-1:0] tx_cal_busy;
- Distribute the PHY reset and calibration busy signals from Transceiver PHY Reset Controller equally to each IP core.
Example: For IP core with two transceiver channels, the tx_analogreset[1:0] is distributed to the link 0 IP core and tx_analogreset[3:2] is distributed to the link 1 IP core.
- Create the mdev_sync_n wire. Example is shown in Verilog HDL:
- wire mdev_sync_n;
- Connect the dev_sync_n port of each IP core to an AND gate. Distribute the output of the AND gate to mdev_sync_n port of each IP core. You can reuse the sync_n wire to connect the dev_sync_n port to the AND gate.
- For combined SYNC_N at the RX subsystem, connect the sync_n_in input port to the sync_n port of each IP core.
- For non-combined SYNC_N at the RX subsystem, scale up the dimension of sync_n_in port to match with the number of links.
output wire [LINK-1:0] sync_n_in,
Assign sync_n_in[index] to each IP core with index as the link number. For example, sync_n_in for Link 0 IP core, sync_n_in for Link 1 IP core.
- Leave the following ports unconnected:
.altera_jesd204_subsystem_tx_altera_jesd204_tx1_csr_tx_testpattern_a_export (/*leave open*/),
- For the rest of the ports, increase the index wires from 0 to 1 and subsequent numbers for the subsequent links.
Example: jesd204_tx_link_data wire should be connected to link 1 IP core and transport layer.
- Because of there is only one PHY reset controller, the tx_ready signal of the subsequent link must be wired to the tx_ready signal of link 0 so that the tx_ready_or_tx_csr_lane_powerdown signal is connected correctly.
generate for (i=1; i<LINK; i=i+1) begin: TX_READY assign xcvr_rst_ctrl_tx_ready[i] = xcvr_rst_ctrl_tx_ready; end endgenerate
- Because of there is only one TX PLL for all the IP cores, copy the transceiver PLL locked status pin for link 1 IP core.
generate for (i=1; i<LINK; i=i+1) begin: XCVR_PLL_LOCKED assign xcvr_pll_locked[i] = xcvr_pll_locked; end endgenerate
- Save the top-level HDL file changes.
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