Viewing the Simulation Results
If the simulation passes, the transcript section prints TESTBENCH_PASSED: SIM PASSED! as shown in the following figure.
If the simulation fails, the transcript section prints TESTBENCH_FAILED: SIM FAILED! along with the failure reason.
If you want to view the waveform, the following are the explanations of a series of events during the link initialization.
- After the /tb_top/rst is de-asserted, the transceiver reset controller sequences the reset for the transceiver in both Link 0 and Link 1 JESD204B IP core.
- The /tb_top/xcvr_rst_ctrl_tx_ready is asserted when the TX transceiver channels and TX PLL are out of reset.
Figure 7. Figure 12. ModelSim‐ Intel® FPGA Edition Simulation Waveform during Global Reset De-assertion
- The TX channels send data to RX channels.
- When the RX channels recovered the data and clock successfully, the /tb_top/xcvr_rst_ctrl_rx_ready is asserted.
- The reset sequencer in the Platform Designer system de-asserts the jesd204_rx_avs_rst_n so that the Avalon-MM BFM master configures the test mode CSR.
- The reset sequencer de-asserts the rxlink_rst_n_reset_n and the IP core is out of reset.
- The RX transport layer asserts the jesd204_rx_link_ready to IP core.
- The testbench sends a rx_sysref pulse to the IP core.
- The IP core de-assert the dev_sync_n.
- After the IP core exits the code group synchronization (CGS) phase, the IP core enters the initial lane alignment sequence (ILAS) phase.
- The alldev_lane_aligned is asserted when both IP cores achieve lane alignment.
- The jesd204_rx_link_valid is asserted when the IP core enters the user data phase and sample data is sent to RX transport layer.
- The RX transport layer performs the lane mapping of the sample data.
- The pattern checker checks the received sample data from RX transport layer.
- No data error is detected by the pattern checker and no interrupt is asserted by both the RX and TX IP cores.
- The testbench asserts the test_passed flag when the above conditions in item 15 are met.
Figure 8. Figure 13. ModelSim‐ Intel® FPGA Edition Simulation Waveform for Successful Link Initialization