AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
Public
Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link

  1. Open the top-level system, altera_jesd204_ed_qsys_TX.qsys, in Platform Designer.
    1. The TX .qsys file is located at ed_sim/testbench/sim_models/ folder.
    2. To open the .qsys file in Platform Designer, you must have an associated Intel® Quartus® Prime project. Copy the altera_jesd204_ed_RX.qpf and altera_jesd204_ed_RX.qsf files from the ed_synth folder into ed_sim/testbench/sim_models folder.
    3. Select the altera_jesd204_ed_RX.qpf and click Open.
    4. The IP Synchronization Result window opens and click OK to proceed.
  2. Disconnect the xcvr_reset_control_0_pll_cal_busy port at the altera_jesd204_subsystem_TX from the pll_cal_busy port at the xcvr_atx_pll_0 component. Export these 2 ports to the top-level.
  3. Each JESD204B link is represented by a single altera_jesd204_subsystem_TX instantiation. To implement multi-link in Platform Designer, right click at the altera_jesd204_subsystem_TX instantiations and select Duplicate.
    You can rename the duplicated module as altera_jesd204_subystem_TX1.
  4. Connect the altera_jesd204_subsystem_TX1 ports as shown in the following table.
    Ports for altera_jesd204_subsystem_TX1 Module Connection
    refclk_xcvr refclk_xcvr.clk 8
    do_not_connect_reset_0 mgmt_clk.clk_reset
    do_not_connect_reset_1 mgmt_clk.clk_reset
    do_not_connect_reset_2 mgmt_clk.clk_reset
    frame_clk frame_clk.clk
    mm_bridge_s0 mm_master_bfm_0.m0
    link_clk link_clk.clk
    mgmt_clk mgmt_clk.clk
    mgmt_reset reset_controller_0.reset_out
    reset_seq_reset_in0 reset_controller_0.reset_out
  5. Leave reset_seq_pll_reset port of the altera_jesd204_subsystem_TX1 module unconnected.
  6. Export the rest of the ports to the top-level Platform Designer system. To export a port, click the Double-click to export in the Export column of the System Contents tab.
  7. At the Address Map, adjust the starting address of altera_jesd204_subsystem_TX1 interface so that there is no conflict with other components. For example, you can set the starting address of altera_jesd204_subsystem_TX1 to 0x0010_0000 as shown in the following table.
    Table 9.  Unsynchronized ADC-FPGA Multi-Link TX Platform Designer Simulation Model Address Map for System Console Control Path
     

    mm_master_bfm_0.m0
    altera_jesd204_subsystem_TX.mm_bridge_s0 0x0000_0000 – 0x000f_ffff
    altera_jesd204_subsystem_TX1.mm_bridge_s0 0x0010_0000 – 0x001f_ffff
  8. Repeat step 3 until step 7 for subsequent links in your design.
  9. Connect the high speed serial clock ports of the duplicated TX IP core to the ATX PLL mgcb_serial_clk port. Example of 2 transceiver channels IP core:
    • altera_jesd204_TX_tx_serial_clk0_ch0
    • altera_jesd204_TX_tx_serial_clk0_ch1
  10. Click Generate HDL.
  11. Ensure you select the HDL language of your choice in the Simulation section of the Generation windows to generate the simulation models.
  12. Click Generate and Yes to save and generate the design files needed for simulation.
  13. After the HDL generation is completed, select Generate from the menu. Select Show Instantiation Template… and click Copy.
  14. Paste the instantiation template of altera_jesd204_ed_qsys_TX Platform Designer to a text editor.
    You must update the instantiated Platform Designer ports at the top-level HDL.
  15. Click Finish to save your Platform Designer settings and exit the Platform Designer window.
8 You cannot share the same transceiver reference clock pin for transceiver channels at different transceiver tiles. For this case, you should instantiate multiple refclk_xcvr clock sources in Platform Designer and connect them to the transceiver reference clock pins at different transceiver tiles.
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