Synchronized ADC- Intel® Stratix® 10 Multi-Link
To synchronize multiple RX IP cores within the Intel® Stratix® 10 device, connect the dev_lane_aligned signal from each IP core with an AND gate. The output of the AND gate connects to the alldev_lane_aligned port of each IP core. The IP cores need to be out of reset simultaneously to complete the link initialization sequence. Multiple IP cores are put into the same JESD204B subsystem so that each IP core’s reset is released by the same reset sequencer simultaneously.
|0||Combined||ANDed and re-distribute||Simultaneous||Refer to Figure 3|
|1||Combined or Non-combined||Refer to Figure 3 and Figure 4|
The SYNC_N signal can be combined or separated within the FPGA. Combining the SYNC_N is mandatory for Subclass 0 subsystem. This is to enable the ADCs to transmit initial lane alignment sequence simultaneously.
For Subclass 1, the SYSREF pulse is the timing reference for the entire JESD204B subsystem. The rise of SYNC_N signals and the transition from code group synchronization (CGS) to initial lane alignment sequence (ILAS) is controlled by the SYSREF. It is important to phase-aligned the SYSREF pulses to the FPGA and converters. Combining SYNC_N is not mandatory unless there is a huge skew beyond one Local Multi-Frame Clock (LMFC) period between the SYNC_N signals to the ADCs.
For Subclass 2, the SYNC_N can be separated and the phase adjustment is between each ADC and IP core pair. Combining SYNC_N has the advantage of ensuring the rise of SYNC_N reaches ADCs at the same time.