Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link
- Open the top-level system, altera_jesd204_ed_qsys_RX.qsys, in Platform Designer.
- The RX .qsys file is located at ed_sim/testbench/models/ folder.
- To open the .qsys file in Platform Designer, you must have an associated Intel® Quartus® Prime project. Copy the altera_jesd204_ed_RX.qpf and altera_jesd204_ed_RX.qsf files from the ed_synth folder into ed_sim/testbench/models folder.
- Select the altera_jesd204_ed_RX.qpf and click Open.
- The IP Synchronization Result window opens and click OK to proceed.
- In the System Contents tab, right-click the altera_jesd204_subsystem_RX instance and select Drill into Subsystem. This opens the altera_jesd204_subsystem_RX Platform Designer subsystem.
- Right-click the altera_jesd204_RX component and select Duplicate.
This duplicates the JESD204B IP core. You can rename the duplicated IP core as altera_jesd204_RX1.Note: Select No if the Platform Designer prompts Do you want to also duplicate the IP Variant file on the disk?. This is because the duplicated JESD204B IP core has the same parameters as the original JESD204B IP core.
- Connect the duplicated IP port as shown in the following table.
- Export the rest of the ports to the top-level Platform Designer system by clicking on the Double-click to export in the Export column of the System Contents tab.
- At the altera_jesd204_RX component, disconnect the connections at the following ports. Export them to the top-level Platform Designer system.
- Change the number of transceiver channels in the Transceiver PHY reset controller to the total number of transceiver channels of all the JESD204B IP cores in the altera_jesd204_subsystem_RX Platform Designer subsystem.
- Exports the following ports from the Transceiver PHY reset controller:
- At the Address Map, adjust the starting address of altera_jesd204_RX1 interface so that there is no conflict with other components. For example, you can set the starting address of altera_jesd204_RX1 IP core to 0x000d_0400 as shown in the following table.
Table 2. Synchronized ADC-FPGA Multi-Link Address Map for System Console Control Path (Dynamic reconfiguration for the PHY is disabled) mm_bridge.m0 altera_jesd204_RX.jesd204_rx_avs 0x000d_0000 – 0x000d_03ff altera_jesd204_RX1.jesd204_rx_avs 0x000d_0400 – 0x000d_07ff Table 3. Synchronized ADC-FPGA Multi-Link Address Map for System Console Control Path (Dynamic reconfiguration for the PHY is enabled) mm_bridge.m0 altera_jesd204_RX.jesd204_rx_avs 0x000d_0000 – 0x000d_03ff altera_jesd204_RX.reconfig_avmm 0x0000_0000 – 0x0000_1fff 3 altera_jesd204_RX1.jesd204_rx_avs 0x000d_0400 – 0x000d_07ff altera_jesd204_RX1.reconfig_avmm 0x0000_2000 – 0x0000_3fff 3
- Repeat step 3 until step 9 for subsequent links in your design.
- Go up to the top-level Platform Designer system.
- Export the rest of unconnected ports of altera_jesd204_subsystem_RX instance.
- Click Generate HDL to generate the design files needed for Intel® Quartus® Prime compilation.
- Ensure you select the HDL language of your choice in the Simulation section of the Generation windows to generate the simulation models.
- Click Generate and Yes to save and generate the design files needed for simulation.
- After the HDL generation is completed, select Generate from the menu. Select Show Instantiation Template… and click Copy.
- Paste the instantiation template of altera_jesd204_ed_qsys_RX Platform Designer to a text editor.
You must update the instantiated Platform Designer ports at the top-level HDL.
- After the HDL generation is completed, click Finish to save your Platform Designer settings and exit the Platform Designer window.
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