AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
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Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link

The simulation testbench, is located at ed_sim/testbench/models folder. Follow these steps to edit the testbench.
  1. Open the testbench ( in a text editor.
  2. Add the LINK parameter at the localparam declaration section. Example:
    localparam LINK = 2;     // Number of IP core in the multi-link design
  3. For non-combined SYNC_N at the RX subsystem, change the dimension of the sync_n wire:
    wire [LINK-1:0] sync_n;
  4. Change the dimension and assignment of the following wires and registers:
    • reg [LINK-1:0] tx_link_error_reg = {LINK{1’b0}};
    • reg [LINK-1:0] rx_link_error_reg = {LINK{1’b0}};
    • reg [LINK-1:0] data_error_reg = {LINK{1’b0}};
    • wire [LINK*L-1:0] tx_serial_data;
    • wire [LINK*L-1:0] rx_serial_data;
    • wire [LINK-1:0] data_valid;
    • wire [LINK-1:0] data_error;
    • wire [LINK-1:0] tx_link_error;
    • wire [LINK-1:0] rx_link_error;
  5. Create the generation loops for the link error and data error signals:
    // Pass/Fail Mechanism
       genvar i;
          for (i=0; i<LINK; i=i+1) begin: LINK_ERROR	
             // Make sure interrupts do not assert
             always @(posedge mgmt_clk or negedge txlink_rst_n) begin
                   tx_link_error_reg[i] <= 1'b0;
                else if (tx_link_error[i])
                   tx_link_error_reg[i] <= 1'b1;
                   tx_link_error_reg[i] <= tx_link_error_reg[i]; 
             always @(posedge mgmt_clk or negedge rxlink_rst_n) begin
                   rx_link_error_reg[i] <= 1'b0;
                else if (rx_link_error[i])
                   rx_link_error_reg[i] <= 1'b1;
                   rx_link_error_reg[i] <= rx_link_error_reg[i];
          for (i=0; i<LINK; i=i+1) begin DATA_ERROR	
    	      always @ (posedge data_error[i]) begin
                if (data_valid[i] == 1'b1)
                   data_error_reg[i] <= 1'b1;
  6. To monitor the combined simulation results of the multi-link, modify the test_passed assignment statement so that if IP core in any of the links has interrupt, the simulation reports failure:
     assign test_passed = (&data_error_reg==1'b0) & (&data_valid==1'b1) & ~(|tx_link_error_reg) & ~(|rx_link_error_reg);
  7. Configure the test mode for the IP cores and link partners in the subsequent links.
    Note: The address in the BFM write/read task consists of base address + IP core register offset. Refer to the Platform Designer address map to set the address in the BFM write/read task for the IP cores in the subsequent links.
    avalon_mm_csr_sim_model_wr(32'h000C04D0, pat_testmode);	// Link 1 CSR
    avalon_mm_csr_dut_wr(32'h000D04D0, pat_testmode);		  // Link 1 CSR
  8. Edit the criteria for displaying link error message for data_error_reg, tx_link_error_reg and rx_link_error_reg signals so that if IP core in any of the links has interrupt, the simulation reports failure. Example:
       if (&data_valid) begin                        
          if (|data_error_reg) begin
             $display("Pattern Checker(s): Data error(s) found!");
          end else begin
             $display("Pattern Checker(s): OK!");
       end else begin
          $display("Pattern Checker(s): No valid data found!");
       if (|tx_link_error_reg) begin
          $display("JESD204B Tx Core(s): Tx link error(s) found!");
       end else begin
          $display("JESD204B Tx Core(s): OK!");
       if (|rx_link_error_reg) begin
          $display("JESD204B Rx Core(s): Rx link error(s) found!");
       end else begin
          $display("JESD204B Rx Core(s): OK!");