AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link

The generate statement in the Verilog HDL file uses the LINK system parameter as an index variable to generate the requisite number of instances for the multi-link use case.
  1. Open the top-level HDL file ( in a text editor.
  2. Modify the LINK system parameter to reflect the number of links in your design.
  3. Insert the newly exported ports from the Platform Designer system at the Platform Designer system instantiation.
  4. Follow these steps to make the connections for the Platform Designer ports:
    1. For SYNC_N, scale up the dimension of sync_n_out port to match with the number of links.
      output wire [LINK-1:0] sync_n_out,
    2. Leave the following ports unconnected:
      • sof
      • somf
      • reset_seq_irq
    3. For the rest of the ports, increase the index of the wires from 0 to 1 and subsequent numbers for the subsequent links.
      For example, jesd204_rx_link_data[1] wire should be connected to link 1 IP core and transport layer.
  5. Save the top-level HDL file changes.
  6. Ensure that any additional pins that are created from the addition of multi-links (for example, rx_serial_data pins) have proper pin assignments in the Intel® Quartus® Prime settings file (altera_jesd204_ed_RX.qsf).
    The transport layer and pattern checker are reset by the reset sequencer in the corresponding altera_jesd204_subsystem_RX and altera_jesd204_subsytem_RX1. No modification is needed at the transport layer and pattern checker generation loops.