AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform

Note: This is an optional step.

You can add the signals of the IP cores in subsequent links to the simulation waveform to monitor the link initialization. For ModelSim‐ Intel® FPGA Edition, include the signals of interest into the file at ed_sim/testbench/mentor folder. Example:

add wave -noupdate -divider {LINK 1}

add wave -noupdate -group {JESD204B BASE CORE 222 L1} {/tb_top/u_altera_jesd204_ed_RX/u_altera_jesd204_ed_qsys_RX/altera_jesd204_subsystem_rx/altera_jesd204_rx1/alldev_lane_aligned}

add wave -noupdate -group {RX TRANSPORT L1}

add wave -noupdate -group {PATTERN CHK L1}