AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Compiling the Design in Intel® Quartus® Prime Software

After modifying the Platform Designer system, top-level HDL file and top-level SDC constraint file, compile the design with the Intel® Quartus® Prime software. Intel® recommends that you perform Analysis and Synthesis and use the RTL Viewer to check the correctness of the connections before fully compile your multi-link design.