AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Document Table of Contents

Simulating the Multi-Link Design

After the modification to the altera_jesd204_ed_qsys_RX.qsys,, altera_jesd204_ed_qsys_TX.qsys, and, you are ready to simulate the multi-link design using the simulator of your choice. The following example uses ModelSim‐ Intel® FPGA Edition.

  1. Launch the ModelSim‐ Intel® FPGA Edition.
  2. At the File menu, select Change Directory.
  3. Select ed_sim/testbench/mentor.
  4. To run the simulation script, type the following command at the transcript prompt:
    do run_tb_top.tcl