AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices

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ID 683725
Date 10/31/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview and Related Information
1. Overview and Related Information x
1.1. Controlled Sequence Designs 1.2. Fault Tolerance 1.3. Driving Unpowered FPGA Pins 1.4. Document Revision History for AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices
1.1. Controlled Sequence Designs x
1.1.1. Programmable Power Management Controller (PPMC) 1.1.2. Low-Cost Discrete Sequencer Design
1.1.1. Programmable Power Management Controller (PPMC) x
1.1.1.1. PPMC Example Design 1.1.1.2. Multiple Supply Sequencer
1.1.2. Low-Cost Discrete Sequencer Design x
1.1.2.1. Low-Cost Sequencer Circuit Description 1.1.2.2. Low-Cost Discrete Sequencer Simulation Results
1.2. Fault Tolerance x
1.2.1. Managing Uncontrolled Loss of Power Events 1.2.2. Sequential vs. Simultaneous Power-Down 1.2.3. Voltage Regulators with Clamping Capability
1.3. Driving Unpowered FPGA Pins x
1.3.1. LVDS I/O Pin Guidance for Unpowered FPGA 1.3.2. Transceiver Pin Guidance for Unpowered FPGA 1.3.3. 3VIO Pin Guidance for Unpowered FPGA
1. Overview and Related Information

1. Overview and Related Information

The Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices require specific power-up and power-down sequences. Intel Agilex® 7 devices require a specific power-up sequence.

The power rails in those devices are each divided into several groups. Refer to the Device Family Pin Connection Guidelines, "Power Management" chapters in the Core Fabric and General Purpose I/Os Handbooks, and the Power Management User Guides for additional details.

For the Power On Reset (POR) delay time specifications, refer to the Device Data Sheets.

Table 1.  Related Information
Title Link
AN 891: Using the Reset Release Intel® Stratix® 10 FPGA IP AN 891: Using the Reset Release Intel® Stratix® 10 FPGA IP
Errata Sheets List of Errata
Intel Agilex® 7 Power Management User Guide Intel Agilex® 7 Power Management User Guide
Intel Agilex® 7 Device Family Pin Connection Guidelines Intel Agilex® 7 Device Family Pin Connection Guidelines
Intel Agilex® 7 Device Data Sheet Intel Agilex® 7 Device Data Sheet
Intel® Stratix® 10 Power Management User Guide Intel® Stratix® 10 Power Management User Guide
Intel® Stratix® 10 Device Family Pin Connection Guidelines Intel® Stratix® 10 Device Family Pin Connection Guidelines
Intel® Stratix® 10 Device Data Sheet Intel® Stratix® 10 Device Data Sheet
Power Management in Intel® Arria® 10 Devices Power Management in Intel® Arria® 10 Devices
Intel® Arria® 10 GX, GT, and SX Pin Connection Guidelines Intel® Arria® 10 GX, GT, and SX Pin Connection Guidelines
Intel® Arria® 10 Device Data Sheet Intel® Arria® 10 Device Data Sheet
Power Management in Intel® Cyclone® 10 GX Devices Power Management in Intel® Cyclone® 10 GX Devices
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Device Data Sheet Intel® Cyclone® 10 GX Device Data Sheet
Quad-Comparator Circuit Provides Power-Down Sequencing At Low Cost How2Power Today, Josh Mandelcorn

Section Content
Controlled Sequence Designs
Fault Tolerance
Driving Unpowered FPGA Pins
Document Revision History for AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, Intel Stratix 10, and Intel Agilex 7 Devices

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