AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices

ID 683725
Date 10/31/2023

1.3.3. 3VIO Pin Guidance for Unpowered FPGA

For the unpowered FPGA, the 3VIO must be in tristate during power-up and power-down. This pin can be in tristate or clamp to GND.