AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Devices

ID 683725
Date 12/07/2022

1.3.3. 3VIO Pin Guidance for Unpowered FPGA

For the unpowered FPGA, the 3VIO must be in tristate during power-up and power-down. This pin can be in tristate or clamp to GND.

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