AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Devices

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ID 683725
Date 10/11/2019
Public

1.3.1. LVDS I/O Pin Guidance for Unpowered FPGA

The LVDS I/O pins do not support ‘Hot-Socketing;’ these LVDS I/O pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per I/O bank. The voltage level of the LVDS I/O pin must not exceed 1.89 V.

A series resistor can be used to help limit current if necessary. The worst case assumption is that VCCIO is unpowered (0 V) while its LVDS I/O pin is driven with a voltage less than the allowable maximum (1.89 V). Refer to the figure below.

Figure 8. LVDS I/O Banks Buffer Structure

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