AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices

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ID 683725
Date 10/31/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview and Related Information
1. Overview and Related Information x
1.1. Controlled Sequence Designs 1.2. Fault Tolerance 1.3. Driving Unpowered FPGA Pins 1.4. Document Revision History for AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices
1.1. Controlled Sequence Designs x
1.1.1. Programmable Power Management Controller (PPMC) 1.1.2. Low-Cost Discrete Sequencer Design
1.1.1. Programmable Power Management Controller (PPMC) x
1.1.1.1. PPMC Example Design 1.1.1.2. Multiple Supply Sequencer
1.1.2. Low-Cost Discrete Sequencer Design x
1.1.2.1. Low-Cost Sequencer Circuit Description 1.1.2.2. Low-Cost Discrete Sequencer Simulation Results
1.2. Fault Tolerance x
1.2.1. Managing Uncontrolled Loss of Power Events 1.2.2. Sequential vs. Simultaneous Power-Down 1.2.3. Voltage Regulators with Clamping Capability
1.3. Driving Unpowered FPGA Pins x
1.3.1. LVDS I/O Pin Guidance for Unpowered FPGA 1.3.2. Transceiver Pin Guidance for Unpowered FPGA 1.3.3. 3VIO Pin Guidance for Unpowered FPGA
1. Overview and Related Information

1.1.1.2. Multiple Supply Sequencer

If only simple power-up/power-down sequencing is required to follow the power sequencing considerations, a low-cost multiple supply sequencer IC can be used.
These devices offer multiple sequenced output enables that are controlled by a dedicated input. When the input is switched on, the Output Enables (EN1/ EN2 /EN3) turn on in successive order after a programmed time delay. This time delay between the output enables can be adjusted.
Figure 2. Example Schematic Design of Multiple Supply IC


Consult your power module vendor for more information about multiple supply sequencer ICs.

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