AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Devices

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ID 683725
Date 10/11/2019
Public

1.4. Document Revision History for AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Devices

Document Version Changes
2019.10.11 Made the following changes:
  • Added references to the correct resources for up-to-date voltage rails and POR specifications.
  • Added Intel® Agilex™ device references.
2019.06.12 Made the following changes:
  • Updated the Managing Uncontrolled Loss of Power Events section.
    • Updated FPGA pin in the "Fault Tolerance Block Diagram".
    • Updated the Theory of Operation section.
    • Updated the "Main Power Loss Detection and Shutdown Event" figure to reflect the removal of nCONFIG and changes to the drop in the power event.
2019.05.20 Made the following changes:
  • Updated VCCIO_UIB power grouping in the "Voltage Rail" table.
2019.03.05 Made the following changes:
  • Added E-tile voltage rails and power-up exception to Power-Up Sequence Requirements.
  • Changed Original Text: For Intel® Cyclone® 10 GX and Intel® Arria® 10 devices, you can combine and ramp up Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as Group 2 power rails VCCIO, VCCPGM, and VCCIO_HPS. to Updated Text: For Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices, you can combine and ramp up Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as Group 2 power rail VCCPT.
  • Changed 1.1 Vp-p references to 1.0 Vp-p.
2018.04.13 Made the following changes:
  • Deleted the note: To satisfy the power-up requirements, program the FPGA device immediately after the power-up sequence completes.
  • Added links to References and moved it to the beginning.
2018.02.28 Made the following changes:
  • Added Intel® Cyclone® 10 GX device support.
  • Added "Sequential vs Simultaneous Power-Down."
  • Added "Voltage Regulators with Clamping Capability."
  • Added "Driving Unpowered FPGA Pins" - "LVDS I/O Pin Guidance for Unpowered FPGA" and "Transceiver Pin Guidance for Unpowered FPGA."
  • Removed Hot-Plug support.
  • Added POR Delay specifications for Intel® Cyclone® 10 GX and Intel® Arria® 10.
2017.05.08 Made the following changes:
  • Added the following description for power-down sequence for Intel® Arria® 10 and Intel® Stratix® 10 devices "For Arria 10 and Stratix 10 devices, when the Group 3 power rails are 1.8V and share the same voltage regulator, then the Group 3 power rails can be combined with Group 2 power rails. In this case, Group 2 and Group 3 power rails can ramp down together." Updated the diagrams accordingly.
  • Added the following note in "Hot-Plug Challenges" topic: "There are hot socket circuits in every 6-pack to monitor VCC, VCCT and VCCR power level. If any of those power supplies are not at operational level, all PMA outputs and inputs are gated low."
2016.10.31 Made the following changes:
  • In the section "Hot Swap Controller and Regulator" updated the description to "When the line card is fully engaged, the card present indicator informs the host that a new card has been successfully inserted. The CONF_DONE signal should then be routed back to the master and sampled as an enable to the signals that are driven. This ensures that configuration is done, the device is stable, and that the master can drive the I/O to the newly powered up slave device without fear of damaging the part. The host system drives the line card's I/O pins and configures it for normal operation."
  • In the "Hot-Plug Example" section added 2 new diagrams for "Hot-Plug Example using Staggered Pin Length Connectors."
2016.09.20 Made the following change:
  • In topic "Power Sequence for Arria 10 and Stratix 10 Devices" for figure "Power-Down Sequence for Arria 10 Devices for combined Group2 and Group3 powers" edited the description to "During the power-up/down sequence, the device output pins are tri-stated. Intel recommends that the input pins should not be driven during this time to ensure long term reliability of the device."
2016.06.16 Made the following changes:
  • Added new figures for "Power-Down Sequence for Arria 10 Devices", "Power-Down Sequence for Stratix 10 Devices" and "Power-Down Sequence for Arria 10 Devices for combined Group2 and Group3 powers".
  • Added the "Power-Up Sequence Considerations for Stratix 10 Devices".
  • Added a new section for "Managing Uncontrolled Loss of Power Events".
  • Added a new figure for "Power-Up Sequence for Stratix 10 Devices".
2015.1.02 Made the following change:
  • Clarified information in the "Power-Up Sequence for Arria 10 Devices" section.
2013.09.06 Initial release to MOLSON.

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