GTS JESD204B IP User Guide

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ID 832100
Date 10/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS JESD204B IP Quick Reference 2. About the GTS JESD204B IP 3. Getting Started 4. GTS JESD204B IP Functional Description 5. GTS JESD204B IP Deterministic Latency Implementation Guidelines 6. GTS JESD204B IP Debug Guidelines 7. Document Revision History for the GTS JESD204B User Guide
2. About the GTS JESD204B IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. GTS JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to IP Cores 3.2. Installing and Licensing IP Cores 3.3. Altera® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. GTS JESD204B IP Design Considerations 3.8. GTS JESD204B IP Parameters 3.9. Analog Parameter Settings 3.10. GTS JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the GTS JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations x
3.7.1. Integrating the GTS JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Configuring the GTS Reset Sequencer IP 3.7.4. REFCLK Recovery (CLK RX)
4. GTS JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Dual Simplex Support 4.4. Operation 4.5. Clocking Scheme 4.6. Reset Scheme 4.7. Signals 4.8. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.4. Operation x
4.4.1. Operating Modes 4.4.2. Scrambler/Descrambler 4.4.3. SYNC_N Signal 4.4.4. Link Reinitialization 4.4.5. Link Startup Sequence 4.4.6. Error Reporting Through SYNC_N Signal
4.4.1. Operating Modes x
4.4.1.1. Subclass 0 Operating Mode 4.4.1.2. Subclass 1 Operating Mode 4.4.1.3. Subclass 2 Operating Mode
4.5. Clocking Scheme x
4.5.1. Device Clock 4.5.2. Link Clock 4.5.3. Local MultiFrame Clock 4.5.4. Clock Correlation 4.5.5. GTS Reset Sequencer IP Clock 4.5.6. HVIO PLL Clocking Mode
4.6. Reset Scheme x
4.6.1. Reset Sequence 4.6.2. TX Reset Entry and Exit Sequence 4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals x
4.7.1. Transmitter Signals 4.7.2. Receiver Signals
4.8. Registers x
4.8.1. Register Access Type Convention 4.8.2. Register Map and Definition 4.8.3. Transmitter Registers 4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. GTS JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B User Guide

1. GTS JESD204B IP Quick Reference

Updated for:
Intel® Quartus® Prime Design Suite 25.3
IP Version 5.0.0

The GTS JESD204B IP is a high-speed point-to-point serial interface intellectual property (IP).

Note: For system requirements and installation instructions, refer to Altera® FPGA Software Installation & Licensing.
Table 1.  Brief Information About the GTS JESD204B IP

Item

Description

Protocol Features
  • Joint Electron Device Engineering Council (JEDEC) JESD204B.01, 2012 standard release specification
  • Device subclass:
    • Subclass 0—Backwards compatible to JESD204A.
    • Subclass 1—Uses SYSREF signal to support deterministic latency.
    • Subclass 2—Uses SYNC_N detection to support deterministic latency.

Core Features
  • Agilex™ 5: Data rate of 2.0 to 19.66 gigabits per second (Gbps)—supports operation beyond JESD204B standard specifications (operation above 12.5 Gbps is outside the scope of JEDEC-defined characterization)
  • Agilex™ 3: Data rate of 2.0 to 12.5 Gbps—per JESD204B specification
  • Single or multiple lanes
    • Supports 1, 2, 4, 6, or 8 lanes per link for Agilex™ 5
    • Supports 1, 2, or 4 lanes per link for Agilex™ 3
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • 8b/10b encoding
  • Scrambling/Descrambling and the option to enable/disable scrambler
    • Supports LSB first serial transmission or MSB first serial transmission
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon® memory-mapped interface for Configuration and Status registers (CSR)
  • Dynamic generation of simulation testbench

Typical Application
  • Wireless communication equipment
  • Broadcast equipment
  • Military equipment
  • Medical equipment
  • Test and measurement equipment

Device Family Support
  • Agilex™ 5 devices
  • Agilex™ 3 devices

Design Tools
  • Platform Designer parameter editor in the Quartus® Prime software for design creation and compilation

  • Timing Analyzer in the Quartus® Prime software for timing analysis

  • ModelSim* - Intel® FPGA Starter Edition, Questa*-Altera® FPGA Starter Edition, QuestaSIM* , Riviera-PRO* , Xcelium* , and VCS* MX simulator software for design simulation
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