GTS JESD204B IP User Guide

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ID 832100
Date 10/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS JESD204B IP Quick Reference 2. About the GTS JESD204B IP 3. Getting Started 4. GTS JESD204B IP Functional Description 5. GTS JESD204B IP Deterministic Latency Implementation Guidelines 6. GTS JESD204B IP Debug Guidelines 7. Document Revision History for the GTS JESD204B User Guide
2. About the GTS JESD204B IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. GTS JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to IP Cores 3.2. Installing and Licensing IP Cores 3.3. Altera® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. GTS JESD204B IP Design Considerations 3.8. GTS JESD204B IP Parameters 3.9. Analog Parameter Settings 3.10. GTS JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the GTS JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations x
3.7.1. Integrating the GTS JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Configuring the GTS Reset Sequencer IP 3.7.4. REFCLK Recovery (CLK RX)
4. GTS JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Dual Simplex Support 4.4. Operation 4.5. Clocking Scheme 4.6. Reset Scheme 4.7. Signals 4.8. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.4. Operation x
4.4.1. Operating Modes 4.4.2. Scrambler/Descrambler 4.4.3. SYNC_N Signal 4.4.4. Link Reinitialization 4.4.5. Link Startup Sequence 4.4.6. Error Reporting Through SYNC_N Signal
4.4.1. Operating Modes x
4.4.1.1. Subclass 0 Operating Mode 4.4.1.2. Subclass 1 Operating Mode 4.4.1.3. Subclass 2 Operating Mode
4.5. Clocking Scheme x
4.5.1. Device Clock 4.5.2. Link Clock 4.5.3. Local MultiFrame Clock 4.5.4. Clock Correlation 4.5.5. GTS Reset Sequencer IP Clock 4.5.6. HVIO PLL Clocking Mode
4.6. Reset Scheme x
4.6.1. Reset Sequence 4.6.2. TX Reset Entry and Exit Sequence 4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals x
4.7.1. Transmitter Signals 4.7.2. Receiver Signals
4.8. Registers x
4.8.1. Register Access Type Convention 4.8.2. Register Map and Definition 4.8.3. Transmitter Registers 4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. GTS JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B User Guide

2.7. Performance and Resource Utilization

Table 5.   GTS JESD204B IP Performance
Device Family FPGA Fabric Speed Grade Data Rate Link Clock FMAX (MHz)
Enable Hard PCS (Gbps) Enable Soft PCS (Gbps)

Agilex™ 5 E-Series (Device Group B1)

 -4 Not supported 2.0 to 17.16 2 data_rate/40
-5 Not supported 2.0 to 16.002 data_rate/40
-6 Not supported 2.0 to 14.252 data_rate/40
Agilex™ 5 E-Series (Device Group A)/D-Series -1 Not supported 2.0 to 19.662 data_rate/40
-2 Not supported 2.0 to 19.662 data_rate/40
-3 Not supported 2.0 to 19.662 data_rate/40
Agilex™ 3 C-Series -6 Not supported 2.0 to 12.502 data_rate/40
-7 Not supported 2.0 to 12.502 data_rate/40

All the variations for resource utilization are configured with the following parameter settings:

Table 6.   Agilex™ 5 Parameter Settings To Obtain the Resource Utilization Data
Parameter Setting
Device A5ED065AB32AI2V
Wrapper Base and PHY
Subclass 1
Data Rate 17.16 Gbps
Bonding Bonded mode
Reference Clock Frequency 260.0 MHz
Octets per frame (F) 1
Enable Scrambler (SCR) Off
Enable Error Code Correction (ECC_EN) Off
Table 7.   Agilex™ 3 Parameter Settings To Obtain the Resource Utilization Data
Parameter Setting
Device A3CW100BM16AI6S
Wrapper Base and PHY
Data rate 12.50 Gbps
Subclass 1
Reference Clock Frequency 250.0 MHz
Bonding Bonded mode
Converter Resolution (N) 16
Transmitted Bits Per Sample (N') 16
Frames Per Multiframe (K) 16
Samples Per Converter Per Frames (S) 1
Enable Scrambler (SCR) OFF
Enable Error Code Correction (ECC_EN) ON
Table 8.   GTS JESD204B IP Core Resource Utilization
Note: The resource utilization data are extracted from a full design which includes the Intel® FPGA Transceiver PHY Reset Controller IP core. Thus, the actual resource utilization for the GTS JESD204B IP core should be smaller by about 15 ALMs and 20 registers.
Device Family Variant L M F ALMs ALUTs Logic Registers M20K
Agilex™ 5 TX 1 4 8 1473.5 1767 1816 1
2 8 8 2504 3225 2930 2
4 8 4 4323.5 5516 5289 4
8 8 4 8121 10390 9775 8
RX 1 4 8 1964 2489 2453 2
2 8 8 3634 4653 4408 4
4 8 4 6695 8643 8235 8
8 8 4 12944.5 16701 15549 16
Agilex™ 3 TX 1 4 8 1527 2023 2084 1
2 8 8 2933.5 3989 3700 2
4 8 4 5439.5 7348 6844 4
RX 1 4 8 1997 2836 2746 2
2 8 8 3582.7 5160 4910 4
4 8 4 6932.2 9806 9282 8
Related Information
1 The data rate for Device Group B can reach a maximum of 17.16 Gbps for speed grade -4 only.
2 This maximum data rate is achieved with ECC disabled, and with different settings, the actual data rate may be lower.
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