AN 114: Board Design Guidelines for Intel Programmable Device Packages

ID 683481
Date 5/27/2022
Document Table of Contents

1. AN 114: Board Design Guidelines for Intel® Programmable Device Packages

As programmable logic devices (PLDs) increase in density and I/O pins, the demand for small packages and diverse packaging options continues to grow. Ball-grid array (BGA) packages are an ideal solution because the I/O connections are on the interior of the device, improving the ratio between pin count and board area. Typical BGA packages contain between two to eight more connections as quad flat pack (QFP) packages. Furthermore, BGA solder balls are considerably stronger than QFP leads, resulting in robust packages that can tolerate rough handling.

This application note provides the recommended PCB design guidelines for some of the more complex package options offered for Intel® Programmable Devices except for Intel® Stratix® 10 devices and beyond.

Note: For more information about Intel® Stratix® 10 device packages and beyond, refer to the respective individual Manufacturing Advantage Services (MAS) Guidelines document.

Did you find the information on this page useful?

Characters remaining:

Feedback Message