AN 114: Board Design Guidelines for Intel Programmable Device Packages

ID 683481
Date 5/27/2022
Public
Document Table of Contents

1.3.3. Signal Line Space and Trace Width

The ability to perform escape routing is defined by the width of the trace and the minimum space required between traces. The minimum area for signal routing is the smallest area that the signal must be routed through (i.e., the distance between two vias, or g in the Escape Routing for Double and Single Traces for 1.00-mm Flip-Chip BGA figure). This area is calculated using the following formula:

g = (BGA pitch) – d

The number of traces that can be routed through this area is based on the permitted line trace and space widths. The following table shows the total number of traces that can be routed through g.

Table 10.  Number of Traces
Number of Traces Formula
1 g >= [2 x (space width)] + trace width
2 g >= [3 x (space width)] + [2 x (trace width)]
3 g >= [5 x (space width)] + [3 x (trace width)]

The following figures show that by reducing the trace and space size, you can route more traces through g. Increasing the number of traces reduces the required number of PCB layers and decreases the overall cost.

Figure 17. Escape Routing for Double and Single Traces for 1.00-mm Flip-Chip BGAThis is not applicable for Intel® Stratix® 10 devices.
Figure 18. Escape Routing for Double and Single Traces for 0.80-mm UBGA (BT Substrate)
Figure 19. Escape Routing for Single Trace for 0.5-mm MBGA

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