AN 114: Board Design Guidelines for Intel Programmable Device Packages

ID 683481
Date 5/27/2022
Public
Document Table of Contents

1.4. Document Revision History for AN 114: Board Design Guidelines for Intel® Programmable Device Packages

Document Version Changes
2022.05.27 Removed instances of Enpirion from AN 114: Board Design Guidelines for Intel® Programmable Device Packages section.
2019.12.31 Added reference links to the following documents:
  • AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
  • AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2019.04.02 Updated the link for the Manufacturing with Intel® Stratix® 10 Field Programmable Gate Arrays document.
2018.10.09
  • Removed Intel® Stratix® 10 information. For more information about Intel® Stratix® 10 packages and beyond, refer to the respective individual Manufacturing Advantage Services (MAS) Guidelines document.
  • Updated the Recommended Pad Sizes for SMD and NSMD Pads table to include 0.80mm UBGA (flip-chip) information.
2018.03.01
  • Rebranded as Intel.
  • Renamed the document as Board Design Guidelines for Intel Programmable Device Packages.
  • Corrected BGA pad opening (A) size of the 0.50 mm MBGA in "Recommended Pad Sizes for SMD and NSMD Pads" table from 0.40 mm to 0.30 mm.
Date Version Changes
February 2017 2017.02.24
  • Added the Sample PCB Routing Scheme on 3 Layers for 0.8-mm 169-pin UBGA section.
  • Added the Sample PCB Routing Scheme on 3 Layers for 0.8-mm 324-pin UBGA section.
  • Updated the Recommended Stratix 10 Stencil Design for the NF43, UF50, and HF55 Package figures.
  • Editorial fix to the Surface Land Pad Dimension section.
  • Editorial fix to the Via Capture Pad Layout and Dimension section.
  • Editorial fix to the Recommended Stratix 10 Pad Pattern (PCB Side) section.
  • Minor text edits.
November 2016 2016.11.23
  • Added the Recommended Stratix 10 Pad Pattern (PCB Side) section.
  • Added the Stratix 10 PCB Manufacturing Recommendation section.
  • Added the Sample PCB Routing Scheme on 2 Layers for 0.5-mm 301-pin MBGA section.
  • Added the Sample PCB Routing Scheme on 3 Layers for 0.5-mm 383-pin MBGA section.
  • Added the Sample PCB Routing Scheme on 6 Layers for 0.5-mm 484-pin MBGA section.
  • Added the NSMD and SMD Pads for Stratix 10 Devices figure.
  • Added the Recommended Pad Sizes for Stratix 10 Devices table to include 1.00 mm (flip-chip) for Stratix 10 devices.
December 2014 2014.12.15
  • Added the Recommended Pad Sizes for WLCSP table.
  • Added the Formula for Via Layouts for 0.5-mm MBGA Land Pads table.
  • Added the Formula for Via Layouts for 0.4-mm VBGA Land Pads table.
  • Added the PCB Vendor Specification for a 0.50-mm MBGA table.
  • Added the PCB Vendor Specification for a 0.40-mm VBGA table.
  • Added the Via and Routing Space Available for 0.50-mm MBGA NSMD Land Pads figure.
  • Added the Placement of Via Capture Pad for 0.5-mm MBGA Land Pads figure.
  • Added the Placement of Via Capture Pad for 0.4-mm VBGA Land Pads figure.
  • Added the Typical Via Capture Pad Size for a 0.50-mm MBGA figure.
  • Added the Typical Via Capture Pad Size for a 0.40-mm VBGA figure.
  • Added the Escape Routing for Single Trace for 0.5-mm MBGA figure.
  • Updated the Via and Routing Space Available for 0.80-mm UBGA (BT Substrate) NSMD Land Pads figure.
September 2014 5.3
  • Dimensions in mm are added to respective figures.
  • PCB Vendor Specifications for 0.80-mm UBGA (BT Substrate) were updated.
  • Sample PCB Routing Scheme on 2 Layers for 0.5mm 153-pin MBGA was added.
  • Sample PCB Routing Scheme on 4 Layers for 0.4mm 81-pin VBGA was added.
  • Sample PCB Routing Scheme on 2 Layers for 0.4mm 36-pin VBGA was added.
January 2014 5.2 0.80-mm UBGA (BT Substrate) package was added.
December 2007 5.1 Additional samples were added in “Number of PCB Layers” on page 15.
May 2007 5.0
  • Updated Table 3 to include pad recommendations for 0.5 mm MBGA.
  • Updated Table 6 to reflect the current PCB vendor capability.
  • Added the MBGA update to “Number of PCB Layers” on page 15 section.
  • Added Figures 16 and 17.
February 2006 4.0 Changed name of document to Designing With High-Density BGA Packages for Altera Devices from Designing With FineLine BGA Packages for APEX, FLEX, ACEX, MAX 7000 & MAX 3000 Devices.

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