Package and Thermal Resistance Information for Devices

Package information includes the ordering code reference, package acronym, leadframe material, lead finish (plating), JEDEC® outline reference, lead coplanarity, weight, moisture sensitivity level, and other special information. The thermal resistance information includes device pin count, package name, and resistance values.

For other devices not listed in the table above, please see the Devices Packaging Datasheet.

Search using Package Drawing Search.

For other related packaging technical information, refer to the following literature.

Packaging
Title
Application Notes
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package
(This application note provides guidelines for handling Altera’s Wafer Level Chip Scale Package (WLCSP) components.)
AN657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices 
(This application note provides guidance on thermal management and mechanical handling of thermal composite flip chip ball-grid array (TCFCBGA) for Altera devices. )
AN659: Thermal Management and Mechanical Handling for Lidless Flip Chip Ball-Grid Array 
(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Altera devices. )
AN 114: Designing with High-Density BGA Packages for Intel Devices
AN 353: SMT Board Assembly Process Recommendations
AN 71: Guidelines for Handling J-Lead, QFP, BGA, FBGA, and Lidless Devices
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