HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus® Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Memory | Mode | Performance | Unit | ||
---|---|---|---|---|---|
–1V | –2V | –3V | |||
MLAB | Single-port RAM/ROM Simple dual-port RAM |
1,000 | 782 | 667 | MHz |
Simple dual-port RAM with read-during-write option set to New Data or Old Data | 630 | 510 | 460 | MHz | |
M20K block108 | Single-port RAM/ROM Simple dual-port RAM |
1,000 | 782 | 667 | MHz |
Simple dual-port RAM, coherent read enabled | 1,000 | 782 | 667 | MHz | |
Single-port RAM with the read-during-write option set to Old Data Simple dual-port RAM with the read-during-write option set to Old Data |
800 | 640 | 560 | MHz | |
Simple dual-port RAM with ECC enabled, 512 × 32 | 600 | 480 | 420 | MHz | |
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 | 1,000 | 782 | 667 | MHz | |
Dual-port ROM True dual-port RAM |
600 | 500 | 420 | MHz | |
Simple quad-port RAM | 600 | 500 | 420 | MHz |
Memory | Mode | Performance | Unit | |||||
---|---|---|---|---|---|---|---|---|
–1V | –2V, –2E | –3V | –4S | –5S | –6S, –6X | |||
MLAB | Single-port RAM/ROM Simple dual-port RAM |
850 | 750 | 510 | 600 | 469 | 400 | MHz |
Simple dual-port RAM with read-during-write option set to New Data or Old Data | 530 | 450 | 380 | 400 | 310 | 280 | MHz | |
M20K block109 | Single-port RAM/ROM Simple dual-port RAM |
1,000 | 782 | 667 | 700 | 550 | 465 | MHz |
Simple dual-port RAM, coherent read enabled | 1,000 | 782 | 667 | 700 | 550 | 465 | MHz | |
Single-port RAM with the read-during-write option set to Old Data Simple dual-port RAM with the read-during-write option set to Old Data |
800 | 640 | 560 | 560 | 440 | 370 | MHz | |
Simple dual-port RAM with ECC enabled, 512 × 32 | 600 | 480 | 420 | 420 | 330 | 280 | MHz | |
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 | 1,000 | 782 | 667 | 700 | 550 | 465 | MHz | |
Dual-port ROM True dual-port RAM |
600 | 500 | 420 | 445 | 335 | 280 | MHz | |
Simple quad-port RAM | 600 | 500 | 420 | 445 | 335 | 280 | MHz |
108 For the M20K block, Quartus® automatically optimizes timing and power based on design requirements.
109 For the M20K block, Quartus® automatically optimizes timing and power based on design requirements.