Agilex™ 5 FPGAs and SoCs Device Data Sheet

Download PDF
ID 813918
Date 10/13/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications

Table 36.  HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) Internal VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-12 1.14 1.2 1.26 0.49 × VCCIO_PIO 0.5 × VCCIO_PIO 0.51 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
HSTL-12 1.14 1.2 1.26 0.47 × VCCIO_PIO 0.5 × VCCIO_PIO 0.53 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
HSUL-1271 1.14 1.2 1.26 0.49 × VCCIO_PIO 0.5 × VCCIO_PIO 0.51 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
POD12 (GPIO)72 73 1.164 1.2 1.236 0.69 × VCCIO_PIO 0.7 × VCCIO_PIO 0.71 × VCCIO_PIO — VCCIO_PIO —
POD12 (PHYLITE)72 73 1.164 1.2 1.236 0.74 × VCCIO_PIO 0.75 × VCCIO_PIO 0.76 × VCCIO_PIO — VCCIO_PIO —
POD11 (GPIO)72 73 1.067 1.1 1.133 0.69 × VCCIO_PIO 0.7 × VCCIO_PIO 0.71 × VCCIO_PIO — VCCIO_PIO —
POD11 (PHYLITE)72 73 1.067 1.1 1.133 0.74 × VCCIO_PIO 0.75 × VCCIO_PIO 0.76 × VCCIO_PIO — VCCIO_PIO —
LVSTL1172 1.067 1.1 1.133 0.24 × VCCIO_PIO 0.25 × VCCIO_PIO 0.26 × VCCIO_PIO — GND —
LVSTL10572 1.0185 1.05 1.0815 0.24 × VCCIO_PIO 0.25 × VCCIO_PIO 0.26 × VCCIO_PIO — GND —
LVSTL700 1.0185 1.05 1.0815 0.174 × VCCIO_PIO 0.184 × VCCIO_PIO 0.194 × VCCIO_PIO — GND —
71 Usage of on-board receiver termination is optional.
72 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
  • PHYLITE mode
  • GPIO mode
73 For I/O lane with mixture of GPIO and PHYLITE interfaces, the VREF specification for that I/O lane follows the PHYLITE VREF specifications.
Level Two Title