Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 8/11/2025
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Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

Recommended Operating Conditions

Table 12.  D-Series FPGAs Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table
Symbol Description Condition Minimum29 Typical Maximum29 Unit
VCC Core voltage supply SmartVID30 : –1V, –2V, –3V (Typical) – 3% 0.70 – 0.9031 (Typical) + 3% V
VCCP Periphery supply voltage for the I/O banks SmartVID30: –1V, –2V, –3V (Typical) – 3% 0.70 – 0.9031 (Typical) + 3% V
VCCH_SDM SDM block transceiver supply voltage sense — 0.975 1 1.025 V
VCCPT 32 Power supply for I/O, DTS, SDM, and system PLL — 1.746 1.8 1.854 V
VCCRCORE Power supply for programmable power technology — 1.14 1.2 1.26 V
VCCBAT 33 Battery back-up power supply (for design security volatile key register) — 1 1 – 1.80 1.8 V
IBAT Battery back-up power supply (for design security volatile key register) VCCBAT = 1.2 V — — 200 nA
VCCIO_PIO_SDM 34 SDM block I/O supply voltage sense of bank 3A 1.2 V 1.164 1.2 1.236 V
VCC_IO_SDM I/O digital supply voltage sense in SDM block SmartVID30: –1V, –2V, –3V (Typical) – 3% 0.70 – 0.9031 (Typical) + 3% V
VCCIO_SDM SDM block configuration pins power supply — 1.71 1.8 1.89 V
VCCL_ADC_SDM Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices SmartVID30: –1V, –2V, –3V (Typical) – 3% 0.70 – 0.9031 (Typical) + 3% V
VCCL_SDM SDM digital power supply — 0.776 0.8 0.824 V
VCCPLLDIG_SDM SDM block PLL digital power supply — 0.776 0.8 0.824 V
VCCPLL_SDM SDM block PLL analog power supply — 1.71 1.8 1.89 V
VCCFUSEWR_SDM Fuse block writing power supply — 1.71 1.8 1.89 V
VCCADC ADC voltage sensor power supply — 1.71 1.8 1.89 V
VCCIO_PIO HSIO bank power supply 1.0 V 0.95 1 1.05 V
1.05 V35 1.0185 1.05 1.0815 V
1.1 V35 1.067 1.1 1.133 V
1.2 V35 1.164 1.2 1.236 V
1.3 V 1.261 1.3 1.339 V
VCCIO_HVIO HVIO bank power supply 3.3 V 3.201 3.3 3.399 V
2.5 V 2.425 2.5 2.575 V
1.8 V 1.746 1.8 1.854 V
VCCPT_HVIO Supply voltage for 1.8 V I/O — 1.746 1.8 1.854 V
VI 36 DC input voltage VCCIO_PIO = 1.0 V37 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.05 V38 37 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.1 V38 37 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.2 V38 37 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.3 V38 37 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_SDM = 1.8 V –0.3000 — VCCIO_SDM + 0.3 V
VCCIO_HPS = 1.8 V –0.3000 — VCCIO_HPS + 0.3 V
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V –0.3000 — VCCIO_HVIO + 0.3 V
VO Output voltage VCCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V 0 — VCCIO_PIO V
VCCIO_SDM = 1.8 V 0 — VCCIO_SDM V
VCCIO_HPS = 1.8 V 0 — VCCIO_HPS V
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V 0 — VCCIO_HVIO V
TJ Operating junction temperature Extended 0 — 10039 °C
Industrial –40 — 10039 °C
tRAMP 40 41 Power supply ramp time Standard POR 200 μs — 100 ms —
Table 13.  E-Series FPGAs Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table
Symbol Description Condition Minimum42 Typical Maximum42 Unit
VCC Core voltage supply SmartVID43 : –1V, –2V, –2E, –3V (Typical) – 3% 0.70 – 0.9044 (Typical) + 3% V
Fixed voltage: –4S 0.776 0.8 0.824 V
Fixed voltage: –5S 0.756 0.78 0.803 V
Fixed voltage: –6S, –6X ​0.7275  ​0.75 ​0.7725  V
VCCP Periphery supply voltage for the I/O banks SmartVID43: –1V, –2V, –2E, –3V (Typical) – 3% 0.70 – 0.9044 (Typical) + 3% V
Fixed voltage: –4S 0.776 0.8 0.824 V
Fixed voltage: –5S 0.756 0.78 0.803 V
Fixed voltage: –6S, –6X ​0.7275  ​0.75 ​0.7725  V
VCCH_SDM SDM block transceiver supply voltage sense SmartVID43: –1V, –2V, –2E, –3V 0.776 0.8 0.824 V
Without transceiver: –4S 0.776 0.8 0.824 V
Without transceiver: –5S 0.756 0.78 0.803 V
Without transceiver: –6S, –6X ​0.7275  ​0.75 ​0.7725  V
With transceiver 0.975 1 1.025 V
VCCPT 45 Power supply for I/O, DTS, SDM, and system PLL — 1.746 1.8 1.854 V
VCCRCORE Power supply for programmable power technology — 1.14 1.2 1.26 V
VCCBAT 46 Battery back-up power supply (for design security volatile key register) — 1 1 – 1.80 1.8 V
IBAT Battery back-up power supply (For design security volatile key register) VCCBAT = 1.2 V — — 200 nA
VCCIO_PIO_SDM 47 SDM block I/O supply voltage sense of bank 3A 1.2 V 1.164 1.2 1.236 V
VCC_IO_SDM I/O digital supply voltage sense in SDM block SmartVID43: –1V, –2V, –2E, –3V (Typical) – 3% 0.70 – 0.9044 (Typical) + 3% V
Fixed voltage: –4S 0.776 0.8 0.824 V
Fixed voltage: –5S 0.756 0.78 0.803 V
Fixed voltage: –6S, –6X ​0.7275  ​0.75 ​0.7725  V
VCCIO_SDM SDM block configuration pins power supply — 1.71 1.8 1.89 V
VCCL_ADC_SDM Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices SmartVID43: –1V, –2V, –2E, –3V (Typical) – 3% 0.70 – 0.9044 (Typical) + 3% V
Fixed voltage: –4S 0.776 0.8 0.824 V
Fixed voltage: –5S 0.756 0.78 0.803 V
Fixed voltage: –6S, –6X ​0.7275  ​0.75 ​0.7725  V
VCCL_SDM SDM digital power supply SmartVID43: –1V, –2V, –2E, –3V 0.776 0.8 0.824 V
Fixed voltage: –4S 0.776 0.8 0.824 V
Fixed voltage: –5S 0.756 0.78 0.803 V
Fixed voltage: –6S, –6X ​0.7275  ​0.75 ​0.7725  V
VCCPLLDIG_SDM SDM block PLL digital power supply SmartVID43: –1V, –2V, –2E, –3V 0.776 0.8 0.824 V
Fixed voltage: –4S 0.776 0.8 0.824 V
Fixed voltage: –5S 0.756 0.78 0.803 V
Fixed voltage: –6S, –6X ​0.7275  ​0.75 ​0.7725  V
VCCPLL_SDM SDM block PLL analog power supply — 1.71 1.8 1.89 V
VCCFUSEWR_SDM Fuse block writing power supply — 1.71 1.8 1.89 V
VCCADC ADC voltage sensor power supply — 1.71 1.8 1.89 V
VCCIO_PIO HSIO bank power supply 1.0 V 0.95 1 1.05 V
1.05 V48 1.0185 1.05 1.0815 V
1.1 V48 1.067 1.1 1.133 V
1.2 V48 1.164 1.2 1.236 V
1.3 V 1.261 1.3 1.339 V
VCCIO_HVIO HVIO bank power supply 3.3 V 3.201 3.3 3.399 V
2.5 V 2.425 2.5 2.575 V
1.8 V 1.746 1.8 1.854 V
VCCPT_HVIO Supply voltage for 1.8 V I/O — 1.746 1.8 1.854 V
VI 49 DC input voltage VCCIO_PIO = 1.0 V50 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.05 V51 50 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.1 V51 50 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.2 V51 50 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.3 V51 50 –0.3000 — VCCIO_PIO + 0.25 V
VCCIO_SDM = 1.8 V –0.3000 — VCCIO_SDM + 0.3 V
VCCIO_HPS = 1.8 V –0.3000 — VCCIO_HPS + 0.3 V
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V –0.3000 — VCCIO_HVIO + 0.3 V
VO Output voltage VCCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V 0 — VCCIO_PIO V
VCCIO_SDM = 1.8 V 0 — VCCIO_SDM V
VCCIO_HPS = 1.8 V 0 — VCCIO_HPS V
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V 0 — VCCIO_HVIO V
TJ Operating junction temperature Extended 0 — 10052 °C
Industrial –40 — 10052 °C
tRAMP 53 54 Power supply ramp time Standard POR 200 μs — 100 ms —
Related Information
29 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
30 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
31 The typical value is based on the SmartVID programmed value.
32 Must use a tolerance of ±3% when sharing with VCCIO_HVIO. A tolerance of ±5% is only allowed when VCCPT is not shared with other rails.
33 Power up VCCBAT with a non-volatile battery power source when using the device security AES BBRAM key. When not using the AES BBRAM key, tie this pin to ground.
34 Must be supplied at 1.2 V when using Avalon® Streaming ×16 configuration schemes. For more information, please refer to the Agilex™ 5 Device Family Pin Connection Guidelines.
35 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes:
  • LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
  • PHYLITE mode
  • GPIO mode
36 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
37 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.
38 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
39 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
40 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies. The ramp time applies to both the ramp-up and ramp-down of the power rails.
41 To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating conditions.
42 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
43 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
44 The typical value is based on the SmartVID programmed value.
45 Must use a tolerance of ±3% when sharing with VCCIO_HVIO. A tolerance of ±5% is only allowed when VCCPT is not shared with other rails.
46 Power up VCCBAT with a non-volatile battery power source when using the device security AES BBRAM key. When not using the AES BBRAM key, tie this pin to ground.
47 Must be supplied at 1.2 V when using Avalon® Streaming ×16 configuration schemes. For more information, please refer to the Agilex™ 5 Device Family Pin Connection Guidelines.
48 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes:
  • LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
  • PHYLITE mode
  • GPIO mode
49 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
50 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.
51 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
52 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
53 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies. The ramp time applies to both the ramp-up and ramp-down of the power rails.
54 To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating conditions.
Level Two Title