Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 10/13/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HPS I2C Timing Characteristics

Table 101.  HPS I2C Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Fclk Serial clock (SCL) clock frequency — 100 — 400 KHz
Tclk Serial clock (SCL) clock period 10 — 2.5 — μs
Tclk_jitter I2C clock output jitter — 2 — 2 %
THIGH 165 SCL high period 4166 — 0.6167 — μs
TLOW 168 SCL low period 4.7169 — 1.3170 — μs
TSU_DAT Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — μs
THD_DAT 171 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
TVD_DAT and TVD_ACK 172 SCL to SDA output data delay — 3.45173 — 0.9174 μs
TSU_STA Setup time for a repeated start condition 4.7 — 0.6 — μs
THD_STA Hold time for a repeated start condition 4 — 0.6 — μs
TSU_STO Setup time for a stop condition 4 — 0.6 — μs
TBUF SDA high pulse duration between STOP and START 4.7 — 1.3 — μs
Tscl_r 175 SCL rise time — 1,000 20 300 ns
Tscl_f 175 SCL fall time — 300 6.54 300 ns
Tsda_r 175 SDA rise time — 1,000 20 300 ns
Tsda_f 175 SDA fall time — 300 6.54 300 ns
Figure 23. I2C Timing Diagram
165 You can adjust THIGH using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
166 The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the SCL_High_time equation in the Hard Processor System Technical Reference Manual.
167 The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the SCL_High_time equation in the Hard Processor System Technical Reference Manual.
168 You can adjust TLOW using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
169 The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the SCL_Low_time equation in the Hard Processor System Technical Reference Manual.
170 The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the SCL_Low_time equation in the Hard Processor System Technical Reference Manual.
171 THD_DAT is affected by the rise and fall time.
172 TVD_DAT and TVD_ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
173 Use maximum SDA_HOLD = 240 to be within the specification.
174 Use maximum SDA_HOLD = 60 to be within the specification.
175 Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value, and total capacitance on the transmission line.
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