Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 10/13/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

MIPI D-PHY I/O Standards Specifications

Table 43.  D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Min Typ Max Min Max Min Max Min Typ Max Min Typ Max
DPHY Applicable for low power when the supported High Speed data rate 150Mbps to 3.5Gbps 1.164 1.2 1.236 — 0.55 0.74 — 1.1 1.2 1.3 –0.05 — 0.05
Applicable for low power when the supported High Speed data rate 150Mbps to 3.5Gbps 1.067 1.1 1.133 0.9585 1.185 1.285
Table 44.  D-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard Condition VCCIO_PIO (V) VID (V) VICM(DC) (V) VOD(DC) (V) VOCM (V) VILHS (V) VIHHS (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min Typ Max Min Max
DPHY Data rate ≤ 1.5 Gbps 1.164 1.2 1.236 0.07 — 0.07 — 0.33 0.14 0.2 0.27 0.15 0.2 0.25 –0.04 0.46
Data rate > 1.5 Gbps to 3.5 Gbps 0.04
Data rate ≤ 1.5 Gbps 1.067 1.1 1.133 0.07
Data rate > 1.5 Gbps to 3.5 Gbps 0.04
Table 45.  E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard Device Group Note VCCIO_PIO (V) VIL (V) VIH (V) VOH (V) VOL (V)
Min Typ Max Min Max Min Max Min Typ Max Min Typ Max
DPHY A Applicable for low power when the supported High Speed data rate 150 Mbps to 3.5 Gbps 1.164 1.2 1.236 — 0.55 0.74 — 1.1 1.2 1.3 –0.05 — 0.05
Applicable for low power when the supported High Speed data rate 150 Mbps to 3.5 Gbps 1.067 1.1 1.133 0.9586 1.186 1.286
B Applicable for low power when the supported High Speed data rate 150 Mbps to 2.5 Gbps 1.164 1.2 1.236 — 0.55 0.74 — 1.1 1.2 1.3 –0.05 — 0.05
Applicable for low power when the supported High Speed data rate 150 Mbps to 2.5 Gbps 1.067 1.1 1.133 0.9586 1.186 1.286
Table 46.  E-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard Condition VCCIO_PIO (V) VID (V) VICM(DC) (V) VOD(DC) (V) VOCM (V) VILHS (V) VIHHS (V)
Device Group Data Rate Min Typ Max Min Max Min Typ Max Min Typ Max Min Typ Max Min Max
DPHY A Data rate ≤ 1.5 Gbps 1.164 1.2 1.236 0.07 — 0.07 — 0.33 0.14 0.2 0.27 0.15 0.2 0.25 –0.04 0.46
Data rate > 1.5 Gbps to 3.5 Gbps 0.04
Data rate ≤ 1.5 Gbps 1.067 1.1 1.133 0.07
Data rate > 1.5 Gbps to 3.5 Gbps 0.04
B Data rate ≤ 1.5 Gbps 1.164 1.2 1.236 0.07 — 0.07 — 0.33 0.14 0.2 0.27 0.15 0.2 0.25 –0.04 0.46
Data rate > 1.5 Gbps to 2.5 Gbps 0.04
Data rate ≤ 1.5 Gbps 1.067 1.1 1.133 0.07
Data rate > 1.5 Gbps to 2.5 Gbps 0.04
85 Receivers compliant to D-PHY v2.1 and later supports a VIH compatible with VOH level regardless of the supported High-Speed data rate.
86 Receivers compliant to D-PHY v2.1 and later supports a VIH compatible with VOH level regardless of the supported High-Speed data rate.
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