HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) |
---|---|---|---|---|
Max | Min | Max | Min | |
SSTL-12 | VREF – 0.075 | VREF + 0.075 | VREF – 0.100 | VREF + 0.100 |
HSTL-12 | VREF – 0.080 | VREF + 0.080 | VREF – 0.150 | VREF + 0.150 |
HSUL-12 | VREF – 0.100 | VREF + 0.100 | VREF – 0.135 | VREF + 0.135 |
POD12 | VREF – 0.055 | VREF + 0.055 | VREF – 0.070 | VREF + 0.070 |
POD11 | VREF – 0.055 | VREF + 0.055 | VREF – 0.070 | VREF + 0.070 |
Note: For output voltage swing calculation example, refer to the General-Purpose I/O User Guide for this device. Differential voltage referenced I/O standard uses two single-ended outputs with second output programmed as inverted.
Note: For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™™ 5 FPGAs and SoCs. The eye mask estimation methodology defined in the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™™ 5 FPGAs and SoCs takes precedence over specifications in HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications table.