Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/11/2025
Public
Document Table of Contents

Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet

Document Version Changes
2025.08.11
  • Updated the minimum VIL and maximum VIN specifications for 2.5 V LVCMOS, 2.5 V LVTTL, 3.3 V LVCMOS, and 3.3 V LVTTL IO standards in the HVIO Single-Ended I/O Standards Specifications table.
  • Added description to the System PLL Reference Clock (Using HVIO) Specifications table.
  • Added Input clock or external feedback clock input duty cycle (tEINDUTY) parameter in the I/O PLL Specifications table.
  • Updated the specifications for TCK clock frequency (FJCP) and TCK clock period (tJCP) in the HPS JTAG Timing Requirements table.
  • Updated the specifications in the Programmable IOE Delay Specifications table.
  • Revised the HPS and SDM DC Characteristics and HPS and SDM I/O Standard Specifications, organizing them into individual sections:
    • HPS I/O DC Characteristics
    • SDM I/O DC Characteristics
    • HPS I/O Standard Specifications
    • SDM I/O Standard Specifications
  • Updated the maximum specifications for Clock Frequency fHSCLK_in(input clock frequency) SLVS400 I/O Standards in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
  • Updated the conditions of Tri-stated pin to VO in the HVIO Pin Leakage Current table.
  • Added footnote about receiver compliance to the VOH in the D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications and E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications tables.
  • Added POD12 and POD11 parameters for GPIO and PHYLITE modes in the HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications table.
  • Added LVSTL700 VREF specifications in the HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications table.
  • Added footnote about POD EMIF Interface to refer to eye mask estimator guidelines in the HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications and HSIO Differential POD I/O Standards Specifications tables.
  • Added notes to the True Differential Signaling-1.3 V (LVDS compatible Transmitter and Receiver) specifications in the HSIO Differential I/O Standards Specifications table.
  • Removed mentions of SLVS in the HSIO OCT Calibration Accuracy Specificationstable.
  • Added SLVS400 I/O standard to the HSIO OCT Without Calibration Resistance Tolerance Specificationstable.
  • Updated the description about overshooting values when using True Differential Signaling I/O standard at VCCIO_PIO at 1.3 V in the Maximum Allowed Overshoot and Undershoot Voltage section.
  • Updated the HDMI 2.1 specifications lane rate in the Electrical Compliance List table.
  • Added OIF-CEI-28G VSR/SR/MR and OIF-CEI-25G protocols to the CEI 4.0 Specification in the Electrical Compliance List table.
  • Updated the footnotes about powering up VCCBAT in the Absolute Maximum Ratings and Recommended Operating Conditionstables.
2025.04.07
  • Updated the footnote and removed LP mode (HS) label for M20K block in the D-Series FPGAs Memory Block Performance Specifications (M20K Block) and E-Series FPGAs Memory Block Performance Specifications (M20K Block) tables.
  • Updated the transmitter tx Jitter and TCCS specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
  • Updated VOD(V) to VOD(DC)(V) in the D-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications and E-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications tables.
  • Removed QDR-IV XP memory standard in the D-Series FPGAs Memory Standards Supported table.
  • Updated the configuration bit stream sizes for A5E005 and A5E007 variants in the Configuration Bit Stream Sizes table.
  • Updated specifications for the HPS and SDM I/O Pin Leakage Current table.
  • Removed Max and Typ specifications for the HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input table.
  • Added notes to the HSIO Single-Ended LVSTL I/O Standards Specifications and HSIO Differential LVSTL I/O Standards Specifications tables.
  • Added footnote for AC input voltage Vi (AC) in the Maximum Allowed Overshoot During Transitions for 1.8 V, 2.5V and 3.3 V in HVIO Bank table.
  • Added note about voltage sensor accuracy specifications in the Voltage Sensor Specifications table.
  • Added SPIM_CLK frequency in the SPI Master Timing Requirements and SPI Slave Timing Requirements tables.
  • Added USB_CLK clock frequency in the following tables:
    • HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements
    • HPS USB 3.1 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements
  • Added Serial Clock (SCL) frequency in the HPS I2C Timing Requirements table.
  • Added Trace clock frequency and updated clock period in the Trace Timing Requirements table.
  • Added TCK clock frequency in the HPS JTAG Timing Requirements table.
  • Updated specifications in the HPS Programmable I/O Delay (Output Path) and HPS Programmable I/O Delay (Input Path) tables.
  • Added footnote for VCO in the -5 and -6 speed grade in the HPS PLL Performance table.
  • Added MDC clock frequency in the Management Data Input/Output (MDIO) Timing Requirements table.
  • Updated SCL clock period (TCLK) specifications in the HPS I3C Push-Pull Timing Requirements for SDR mode table.
  • Added SCL high period (for First Broadcast Address) specification in the HPS I3C Open Drain Timing Requirements table.
  • Updated the description of VCCH_SDM in the Recommended Operating Conditions and Absolute Maximum Ratings tables.
2025.01.23
  • Updated the 9x9 and 27x27 specifications in the D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks and E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks) tables.
  • Updated Internal VREF specifications for LVSTL700, LVSTL105 and LVSTL11 I/O standards in the HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications table.
  • Updated the maximum data rate for True Differential Signaling I/O standards – fHSDR (data rate) when using LVDS SERDES factor J=1 and J=2 in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
  • Added the configuration bit stream sizes for A5D 051 and A5D 064 variants in Configuration Bit Stream Sizes table.
2024.11.25
  • Updated the minimum value of Text_delay symbol in the AS Timing Parameters table.
  • Update the maximum data rate for LVDS SERDES Receiver specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
  • Minor update on the description in the HVIO Hysteresis Specifications for Schmitt Trigger Input table.
  • Updated the maximum frequency of DDR4 SDRAM Memory Standards in the D-Series FPGAs Memory Standards Supported and E-Series Device Group B FPGAs Memory Standards Supported tables.
  • Minor update in the footnote for the Voltage Sensor Specifications table.
  • Updated the fHSDR data rate (without DPA) in SERDES factor J = 4 and 8 specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
  • Updated the clause used to IEEE 802.3by for 25GAUI-C2C/C2M in the Electrical Compliance List table.
  • Updated the Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] (Th) specifications in the HPS USB UPLI Timing Characteristics table.
2024.08.05
  • Added note on 100 ohm for VCCIO_PIO in HSIO OCT Without Calibration Resistance Tolerance Specifications table.
  • Updated the minimum timing parameters for tADSU and tAVSU symbols in Avalon Streaming Timing Parameters for x8 and x16 Configurations table.
  • Updated the specifications in HVIO I/O Pin Leakage Current table.
  • Updated the specifications in HVIO Internal Weak Pull-Up and Pull Down Resistor Value table.
  • Updated the specifications in D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications and E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications tables.
  • Updated the specifications in the -E6S, -I6S, -E6X and -I6X speed grade in Programmable IOE Delay Specifications table.
  • Updated the LPDDR5 SDRAM Memory Standard parameters in E-Series Device Group B FPGAs Memory Standards Supported table.
  • Added footnote for Receiver DPA mode with J-factor 4 and 8 for all speed grade at maximum corner data rates in the following tables:
    • D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications
    • E-Series Device Group B FPGAs LVDS SERDES Specifications
  • Updated the Typical values in the HPS Programmable I/O Delay (Output Path) and HPS Programmable I/O Delay (Input Path) tables.
  • Updated tINCCJ specifications to ±750 ps in I/O PLL Specifications table.
  • Added CML and HSCL as the supported I/O standards in GTS Transceiver and System PLL Reference Clock Input Specifications table.
2024.04.01 Initial release.
2023.08.11
  • Updated the D-Series FPGAs Absolute Maximum Ratings table.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Added VCCIO_PIO specifications for VCCIO_PIO = 1.0 V.
    • Updated VI specifications and footnote.
    • Updated IOUT specifications and added footnote.
  • Updated the E-Series FPGAs Absolute Maximum Ratings table.
    • Updated –6L to –6X speed grade.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Added VCCIO_PIO specifications for VCCIO_PIO = 1.0 V.
    • Updated VI specifications and footnote.
    • Updated IOUT specifications and added footnote.
  • Updated the description in the Maximum Allowed Overshoot and Undershoot Voltage section and added the following tables:
    • Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank
    • Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank
  • Updated the D-Series FPGAs Recommended Operating Conditions table.
    • Updated VCCIO_PIO_SDM specifications.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Updated VCCIO_PIO specifications and footnote.
    • Updated VI specifications and footnote.
    • Added VO specifications for VCCIO_PIO = 1.0 V.
    • Updated tRAMP footnote.
  • Updated the E-Series FPGAs Recommended Operating Conditions table.
    • Updated –6L to –6X speed grade.
    • Updated VCCH_SDM, VCCIO_PIO_SDM, and VCC_IO_SDM specifications.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Updated VCCIO_PIO specifications and footnote.
    • Updated VI specifications and footnote.
    • Added VO specifications for VCCIO_PIO = 1.0 V.
    • Updated tRAMP footnote.
  • Added footnote to maximum value column in the D-Series FPGAs GTS Transceiver Power Supply Operating Conditions table.
  • Updated the E-Series FPGAs GTS Transceiver Power Supply Operating Conditions table.
    • Added footnote to maximum value column.
    • Updated –6L to –6X speed grade.
  • Updated the HSIO OCT Calibration Accuracy Specifications table.
    • Removed 50-Ω RS specification.
    • Added footnote to RS and RT.
    • Removed DPHY11 I/O standards support.
  • Updated the HSIO OCT Without Calibration Resistance Tolerance Specifications table.
    • Added 34-Ω and 40-Ω RS specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards.
    • Added footnote to RS and RT.
  • Added specifications for VCCIO_PIO = 1.0 ±5% and VCCIO_PIO = 1.3 ±5% in the HSIO Internal Weak Pull-Up Resistor table.
  • Updated II and IOZ specifications for VI = 0 V to VCCIO_HVIO = 2.5 V in the HVIO I/O Pin Leakage Current table.
  • Updated CIO specification in the HVIO Pin Capacitance table.
  • Updated VHYS specification for VCCIO_HVIO = 3.3 V in the HVIO Hysteresis Specifications for Schmitt Trigger Input table.
  • Added specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards in the HSIO Single-Ended I/O Standards Specifications table.
  • Updated POD11 and POD12 specifications in the HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications table.
  • Updated LVSTL11, LVSTL105, and LVSTL700 specifications in the HSIO Single-Ended LVSTL I/O Standards Specifications table.
  • Added footnote to SSTL-12, HSTL-12, and HSUL-12 in the HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications table.
  • Updated POD11 and POD12 specifications in the HSIO Differential POD I/O Standards Specifications table.
  • Updated LVSTL11, LVSTL105, and LVSTL700 specifications in the HSIO Differential LVSTL I/O Standards Specifications table.
  • Updated fIN specifications in the D-Series FPGAs I/O PLL Specifications table.
  • Updated the E-Series FPGAs I/O PLL Specifications table.
    • Updated fIN specifications.
    • Updated –6L to –6X speed grade.
  • Updated Fixed-point complex multiplication mode to Fixed-point 18 x 19 complex multiplication mode in the D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks table.
  • Updated –6L to –6X speed grade in the E-Series FPGAs DSP Block Performance Specifications for Single DSP Block table.
  • Updated the E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks table.
    • Updated –6L to –6X speed grade.
    • Updated Fixed-point complex multiplication mode to Fixed-point 18 x 19 complex multiplication mode.
  • Updated –6L to –6X speed grade in the E-Series FPGAs Memory Block Performance Specifications table.
  • Updated the Voltage Sensor Specifications table.
    • Added external reference voltage specifications.
    • Updated footnote to voltage sensor accuracy, Vin.
  • Split the LVDS SERDES Specifications table into the following tables and updated specifications:
    • D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications
    • E-Series Device Group B FPGAs LVDS SERDES Specifications
  • Removed TPP-JITTER-TOLERANCE specifications in the System PLL Reference Clock (Using HVIO) Specifications table.
  • Updated the Electrical Compliance List table.
    • Updated specification for IEEE 802.3by 111/110 and CPRI V7.0.
    • Added footnote to PCIe BASE 4.0 / PIPE 4.4.1 specification.
    • Updated specification/clause and protocol for USB.
  • Removed the following RMII content:
    • Reduced Media Independent Interface (RMII) Clock Timing Requirements table
    • RMII TX Timing Requirements table
    • RMII TX Timing Diagram
    • RMII RX Timing Requirements table
    • RMII RX Timing Diagram
  • Removed ONFI 3.x, INFI 4.x, NV-DDR2, and NV-DDR3 in the table description of the following tables:
    • HPS NAND SDR Timing Requirements
    • HPS NAND DDR Timing Requirements
  • Updated tJCP, tJCH, tJCL, tJPSU (TMS), tJPH, tJPCO, tJPZX, and tJPXZ specifications in the JTAG Timing Parameters and Values table.
  • Updated tACLKH, tACLKL, tACLKP, tADSU, tADH, and tAVSU specifications in the Avalon Streaming Timing Parameters for ×8 and ×16 Configurations table.
  • Updated the Programmable IOE Delay Specifications table.
    • Added specifications for Output Enable Delay Chain (OUTPUT_EENABLE_DELAY_CHAIN).
    • Updated –6L to –6X speed grade.
2023.03.27 Initial release.