Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HPS Power Supply Operating Conditions

Table 16.  D-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table
Symbol Description Condition Minimum Typical Maximum Unit
VCCL_HPS HPS DSU voltage and periphery circuitry power supply SmartVID: –1V, –2V, –3V59 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCL_HPS_CORE0_CORE1 HPS Cortex*-A55 core 0 and core 1 power rail SmartVID: –1V, –2V, –3V59 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCL_HPS_CORE2 HPS Cortex*-A76 core 2 power rail SmartVID: –1V, –2V, –3V59 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCL_HPS_CORE3 HPS Cortex*-A76 core 3 power rail SmartVID: –1V, –2V, –3V59 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLLDIG1_HPS HPS PLL1 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –3V59 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLLDIG2_HPS HPS PLL2 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –3V59 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLL1_HPS HPS PLL1 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCPLL2_HPS HPS PLL2 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCIO_HPS HPS I/O buffers power supply 1.8 V 1.71 1.8 1.89 V
Table 17.  E-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table
Symbol Description Condition Minimum Typical Maximum Unit
VCCL_HPS HPS DSU voltage and periphery circuitry power supply SmartVID: –1V, –2V, –2E, –3V60 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCL_HPS_CORE0_CORE1 HPS Cortex*-A55 core 0 and core 1 power rail SmartVID: –1V, –2V, –2E, –3V60 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCL_HPS_CORE2 HPS Cortex*-A76 core 2 power rail SmartVID: –1V, –2V, –2E, –3V60 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCL_HPS_CORE3 HPS Cortex*-A76 core 3 power rail SmartVID: –1V, –2V, –2E, –3V60 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCPLLDIG1_HPS HPS PLL1 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –2E, –3V60 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCPLLDIG2_HPS HPS PLL2 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –2E, –3V60 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCPLL1_HPS HPS PLL1 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCPLL2_HPS HPS PLL2 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCIO_HPS HPS I/O buffers power supply 1.8 V 1.71 1.8 1.89 V
Related Information
59 The use of Power Management Bus (PMBus*) voltage regulator dedicated to the SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
60 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
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