Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

I/O PLL Specifications

Table 52.  D-Series FPGAs I/O PLL Specifications For specification status, see the Data Sheet Status table
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency source from core clock input and reference clock input –1V 10 — 1,10090 MHz
–2V 10 — 90090 MHz
–3V 10 — 62590 MHz
Input clock frequency source from HSIO clock input –1V 10 — 80090 MHz
–2V 10 — 71790 MHz
–3V 10 — 62590 MHz
Input clock frequency source from HVIO clock input — 10 — 156.2590 MHz
fINPFD Input clock frequency to the PFD — 10 — 325 MHz
fVCO I/O PLL VCO operating range –1V 600 — 3,200 MHz
–2V 600 — 3,200 MHz
–3V 600 — 2,400 MHz
fCLBW I/O PLL closed-loop bandwidth — 0.5 — 20 MHz
fOUT Output frequency for internal clock (C counter) –1V — — 1,100 MHz
–2V — — 1,000 MHz
–3V — — 780 MHz
fOUT_EXT Output frequency for external clock output –1V — — 800 MHz
–2V — — 717 MHz
–3V — — 625 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz 45 50 55 %
fOUT_EXT ≥ 300 MHz 40/45 91 50 55 91/60 %
tFCOMP 92 External feedback clock compensation time — — — 5 ns
fDYCONFIGCLK Dynamic configuration clock — — — 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
tPLL_PSERR 93 Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on the areset signal — 10 — — ns
tINCCJ Input clock cycle-to-cycle jitter fREF < 100 MHz 94 — — ±750 ps (p-p)
fREF ≥ 100 MHz 94 — — 0.15 UI (p-p)
tREFPJ Reference phase jitter (rms)95 Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz — — 1.42 ps
tREFPN Reference phase noise96 95 10 Hz — — –90 dBc/Hz
100 Hz — — –100 dBc/Hz
1 kHz — — –110 dBc/Hz
10 kHz — — –120 dBc/Hz
100 kHz — — –130 dBc/Hz
1 MHz — — –138 dBc/Hz
10 MHz — — –142 dBc/Hz
100 MHz — — –144 dBc/Hz
tOUTPJ_DC 92 97 Period jitter for dedicated clock output fOUT < 100 MHz 94 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 94 — — 175 ps (p-p)
tOUTCCJ_DC 92 97 Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz 94 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 94 — — 175 ps (p-p)
tOUTPJ_IO 98 97 Period jitter for clock output on the regular I/O fOUT < 100 MHz 94 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 94 — — 600 ps (p-p)
tOUTCCJ_IO 98 97 Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz 94 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 94 — — 600 ps (p-p)
tCASC_OUTPJ_DC 92 Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz 94 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 94 — — 175 ps (p-p)
tEINDUTY Input clock or external feedback clock input duty cycle fIN ≥ 600 MHz 30 — 70 %
450 MHz ≤ fIN < 600 MHz 35 — 65 %
250 MHz ≤ fIN < 450 MHz 40 — 60 %
10 MHz ≤ fIN < 250 MHz 45 — 55 %
Table 53.  E-Series FPGAs I/O PLL Specifications For specification status, see the Data Sheet Status table
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency source from core clock input and reference clock input –1V, –4S 10 — 1,10099 MHz
–2V, –2E, –5S 10 — 90099 MHz
–3V, –6S, –6X 10 — 62599 MHz
Input clock frequency source from HSIO clock input –1V, –4S 10 — 80099 MHz
–2V, –2E, –5S 10 — 71799 MHz
–3V, –6S, –6X 10 — 62599 MHz
Input clock frequency source from HVIO clock input — 10 — 156.2599 MHz
fINPFD Input clock frequency to the PFD — 10 — 325 MHz
fVCO I/O PLL VCO operating range –1V, –4S 600 — 3,200 MHz
–2V, –2E, –5S 600 — 3,200 MHz
–3V, –6S, –6X 600 — 2,400 MHz
fCLBW I/O PLL closed-loop bandwidth — 0.5 — 20 MHz
fOUT Output frequency for internal clock (C counter) –1V,–4S — — 1,100 MHz
–2V, –2E, –5S — — 1,000 MHz
–3V, –6S, –6X — — 780 MHz
fOUT_EXT Output frequency for external clock output –1V, –4S — — 800 MHz
–2V, –2E, –5S — — 717 MHz
–3V, –6S, –6X — — 625 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz 45 50 55 %
fOUT_EXT ≥ 300 MHz 40/45 100 50 55 100/60 %
tFCOMP 101 External feedback clock compensation time — — — 5 ns
fDYCONFIGCLK Dynamic configuration clock — — — 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
tPLL_PSERR 102 Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on the areset signal — 10 — — ns
tINCCJ Input clock cycle-to-cycle jitter fREF < 100 MHz 103 — — ±750 ps (p-p)
fREF ≥ 100 MHz 103 — — 0.15 UI (p-p)
tREFPJ Reference phase jitter (rms)104 Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz — — 1.42 ps
tREFPN Reference phase noise105 104 10 Hz — — –90 dBc/Hz
100 Hz — — –100 dBc/Hz
1 kHz — — –110 dBc/Hz
10 kHz — — –120 dBc/Hz
100 kHz — — –130 dBc/Hz
1 MHz — — –138 dBc/Hz
10 MHz — — –142 dBc/Hz
100 MHz — — –144 dBc/Hz
tOUTPJ_DC 101 106 Period jitter for dedicated clock output fOUT < 100 MHz 103 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 103 — — 175 ps (p-p)
tOUTCCJ_DC 101 106 Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz 103 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 103 — — 175 ps (p-p)
tOUTPJ_IO 107 106 Period jitter for clock output on the regular I/O fOUT < 100 MHz 103 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 103 — — 600 ps (p-p)
tOUTCCJ_IO 107 106 Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz 103 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 103 — — 600 ps (p-p)
tCASC_OUTPJ_DC 101 Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz 103 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 103 — — 175 ps (p-p)
tEINDUTY Input clock or external feedback clock input duty cycle fIN ≥ 600 MHz 30 — 70 %
450 MHz ≤ fIN < 600 MHz 35 — 65 %
250 MHz ≤ fIN < 450 MHz 40 — 60 %
10 MHz ≤ fIN < 250 MHz 45 — 55 %
Related Information
90 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
91 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to the Clocking and PLL User Guide for the detail design guidelines.
92 Not applicable for fabric-feeding I/O PLL.
93 PLL phase shift accuracy is 50 ps with the assumption of fVCO = 1.6 GHz.
94 fREF is fIN/N, specification applies when N = 1.
95 Requirement for DDR/LPDDR protocol and LVDS SERDES applications only.
96 The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
97 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Clocking and PLL User Guide for the recommended spread-spectrum clock profile.
98 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output clock Jitter Specifications table.
99 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
100 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to the Clocking and PLL User Guide for the detail design guidelines.
101 Not applicable for fabric-feeding I/O PLL.
102 PLL phase shift accuracy is 50 ps with the assumption of fVCO = 1.6 GHz.
103 fREF is fIN/N, specification applies when N = 1.
104 Requirement for DDR/LPDDR protocol and LVDS SERDES applications only.
105 The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
106 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Clocking and PLL User Guide for the recommended spread-spectrum clock profile.
107 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output clock Jitter Specifications table.
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