AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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ID 683657
Date 12/18/2017
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Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

The Intel FPGA JESD204B IP Core is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) devices.

This report highlights the interoperability of the JESD204B IP core with the AD9208 converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results.

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