- Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Receiver Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization (ILA).
On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The Signal Tap II Logic Analyzer tool monitors the receiver data link layer operation.
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