AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

ID 683657
Date 12/18/2017

Receiver Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization (ILA).

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The Signal Tap II Logic Analyzer tool monitors the receiver data link layer operation.