AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Test Results

The following table contains the possible results and their definition.

Table 7.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.
The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, TL.2, SCR.1, and SCR.2 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.
Table 8.  Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, TL.2, SCR.1, and SCR.2
Test L M F SCR K Data rate (Gbps) ADC Sampling Clock (MHz) Link Clock (MHz) Result
1 1 1 2 0 32 16 800 400 PASS
2 1 1 2 1 32 16 800 400 PASS
3 1 1 2 0 16 16 800 400 PASS
4 1 1 2 1 16 16 800 400 PASS
1 1 1 4 0 32 16 800 400 PASS
2 1 1 4 1 32 16 800 400 PASS
3 1 1 4 0 16 16 800 400 PASS
4 1 1 4 1 16 16 800 400 PASS
1 2 1 1 0 32 16 1600 400 PASS
2 2 1 1 1 32 16 1600 400 PASS
3 2 1 1 0 20 16 1600 400 PASS
4 2 1 1 1 20 16 1600 400 PASS
1 2 1 2 0 32 16 1600 400 PASS
2 2 1 2 1 32 16 1600 400 PASS
3 2 1 2 0 16 16 1600 400 PASS
4 2 1 2 1 16 16 1600 400 PASS
1 4 1 1 0 32 15 3000 375 PASS
2 4 1 1 1 32 15 3000 375 PASS
3 4 1 1 0 20 15 3000 375 PASS
4 4 1 1 1 20 15 3000 375 PASS
1 4 1 2 0 32 15 3000 375 PASS
2 4 1 2 1 32 15 3000 375 PASS
3 4 1 2 0 16 15 3000 375 PASS
4 4 1 2 1 16 15 3000 375 PASS
1 8 1 1 0 32 7.5 3000 187.5 PASS
2 8 1 1 1 32 7.5 3000 187.5 PASS
3 8 1 1 0 20 7.5 3000 187.5 PASS
4 8 1 1 1 20 7.5 3000 187.5 PASS
1 8 1 2 0 32 7.5 3000 187.5 PASS
2 8 1 2 1 32 7.5 3000 187.5 PASS
3 8 1 2 0 16 7.5 3000 187.5 PASS
4 8 1 2 1 16 7.5 3000 187.5 PASS
1 1 2 4 0 32 16 400 400 PASS
2 1 2 4 1 32 16 400 400 PASS
3 1 2 4 0 16 16 400 400 PASS
4 1 2 4 1 16 16 400 400 PASS
1 1 2 8 0 32 16 400 400 PASS
2 1 2 8 1 32 16 400 400 PASS
3 1 2 8 0 16 16 400 400 PASS
4 1 2 8 1 16 16 400 400 PASS
1 2 2 2 0 32 16 800 400 PASS
2 2 2 2 1 32 16 800 400 PASS
3 2 2 2 0 16 16 800 400 PASS
4 2 2 2 1 16 16 800 400 PASS
1 2 2 4 0 32 16 800 400 PASS
2 2 2 4 1 32 16 800 400 PASS
3 2 2 4 0 16 16 800 400 PASS
4 2 2 4 1 16 16 800 400 PASS
1 4 2 1 0 32 16 1600 400 PASS
2 4 2 1 1 32 16 1600 400 PASS
3 4 2 1 0 20 16 1600 400 PASS
4 4 2 1 1 20 16 1600 400 PASS
1 4 2 2 0 32 16 1600 400 PASS
2 4 2 2 1 32 16 1600 400 PASS
3 4 2 2 0 16 16 1600 400 PASS
4 4 2 2 1 16 16 1600 400 PASS
1 8 2 1 0 32 15 3000 375 PASS
2 8 2 1 1 32 15 3000 375 PASS
3 8 2 1 0 20 15 3000 375 PASS
4 8 2 1 1 20 15 3000 375 PASS
1 8 2 2 0 32 15 3000 375 PASS
2 8 2 2 1 32 15 3000 375 PASS
3 8 2 2 0 16 15 3000 375 PASS
4 8 2 2 1 16 15 3000 375 PASS
1 1 4 8 0 32 16 400 400 PASS
2 1 4 8 1 32 16 400 400 PASS
3 1 4 8 0 16 16 400 400 PASS
4 1 4 8 1 16 16 400 400 PASS
1 2 4 4 0 32 16 800 400 PASS
2 2 4 4 1 32 16 800 400 PASS
3 2 4 4 0 16 16 800 400 PASS
4 2 4 4 1 16 16 800 400 PASS
1 2 4 8 0 32 16 800 400 PASS
2 2 4 8 1 32 16 800 400 PASS
3 2 4 8 0 16 16 800 400 PASS
4 2 4 8 1 16 16 800 400 PASS
1 4 4 2 0 32 16 1600 400 PASS
2 4 4 2 1 32 16 1600 400 PASS
3 4 4 2 0 16 16 1600 400 PASS
4 4 4 2 1 16 16 1600 400 PASS
1 4 4 4 0 32 16 1600 400 PASS
2 4 4 4 1 32 16 1600 400 PASS
3 4 4 4 0 16 16 1600 400 PASS
4 4 4 4 1 16 16 1600 400 PASS
1 8 4 1 0 32 15 3000 375 PASS
2 8 4 1 1 32 15 3000 375 PASS
3 8 4 1 0 20 15 3000 375 PASS
4 8 4 1 1 20 15 3000 375 PASS
1 8 4 2 0 32 15 3000 375 PASS
2 8 4 2 1 32 15 3000 375 PASS
3 8 4 2 0 16 15 3000 375 PASS
4 8 4 2 1 16 15 3000 375 PASS
1 2 8 8 0 32 16 400 400 PASS
2 2 8 8 1 32 16 400 400 PASS
3 2 8 8 0 16 16 400 400 PASS
4 2 8 8 1 16 16 400 400 PASS
1 4 8 4 0 32 16 800 400 PASS
2 4 8 4 1 32 16 800 400 PASS
3 4 8 4 0 16 16 800 400 PASS
4 4 8 4 1 16 16 800 400 PASS
1 4 8 8 0 32 16 800 400 PASS
2 4 8 8 1 32 16 800 400 PASS
3 4 8 8 0 16 16 800 400 PASS
4 4 8 8 1 16 16 800 400 PASS
1 8 8 2 0 32 16 1600 400 PASS with comments 5
2 8 8 2 1 32 16 1600 400 PASS with comments 5
3 8 8 2 0 16 16 1600 400 PASS
4 8 8 2 1 16 16 1600 400 PASS
1 8 8 4 0 32 16 1600 400 PASS with comments 5
2 8 8 4 1 32 16 1600 400 PASS with comments 5
3 8 8 4 0 16 16 1600 400 PASS
4 8 8 4 1 16 16 1600 400 PASS

The following table shows the results for test cases DL.1, DL.2, DL.3 and DL.4 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies.

Table 9.  Results for Deterministic Latency Test
Test L M F Subclass K Data rate (Gbps) Sampling Clock(MHz) Link Clock (MHz) Result

Latency

(Link Clock Cycles)
DL.1 1 1 2 1 16/32 16 800 400 PASS

75 (K=16)

115 (K=32)
DL.2 1 1 2 1 16/32 16 800 400 PASS
DL.3 1 1 2 1 16/32 16 800 400 PASS
DL.4 1 1 2 1 16/32 16 800 400 PASS
DL.1 1 1 4 1 16/32 16 800 400 PASS

115 (K=16)

195 (K=32)
DL.2 1 1 4 1 16/32 16 800 400 PASS
DL.3 1 1 4 1 16/32 16 800 400 PASS
DL.4 1 1 4 1 16/32 16 800 400 PASS
DL.1 2 1 1 1 20/32 16 1600 400 PASS

58 (K=20)

67 (K=32)
DL.2 2 1 1 1 20/32 16 1600 400 PASS
DL.3 2 1 1 1 20/32 16 1600 400 PASS
DL.4 2 1 1 1 20/32 16 1600 400 PASS
DL.1 2 1 2 1 16/32 16 1600 400 PASS

73 (K=16)

103 (K=32)
DL.2 2 1 2 1 16/32 16 1600 400 PASS
DL.3 2 1 2 1 16/32 16 1600 400 PASS
DL.4 2 1 2 1 16/32 16 1600 400 PASS
DL.1 4 1 1 1 20/32 15 3000 375 PASS

53 (K=20)

67 (K=32)
DL.2 4 1 1 1 20/32 15 3000 375 PASS
DL.3 4 1 1 1 20/32 15 3000 375 PASS
DL.4 4 1 1 1 20/32 15 3000 375 PASS
DL.1 4 1 2 1 16/32 15 3000 375 PASS

67 (K=16)

99 (K=32)
DL.2 4 1 2 1 16/32 15 3000 375 PASS
DL.3 4 1 2 1 16/32 15 3000 375 PASS
DL.4 4 1 2 1 16/32 15 3000 375 PASS
DL.1 8 1 1 1 20/32 7.5 3000 187.5 PASS

53 (K=20)

67 (K=32)
DL.2 8 1 1 1 20/32 7.5 3000 187.5 PASS
DL.3 8 1 1 1 20/32 7.5 3000 187.5 PASS
DL.4 8 1 1 1 20/32 7.5 3000 187.5 PASS
DL.1 8 1 2 1 16/32 7.5 3000 187.5 PASS

67 (K=16)

99 (K=32)
DL.2 8 1 2 1 16/32 7.5 3000 187.5 PASS
DL.3 8 1 2 1 16/32 7.5 3000 187.5 PASS
DL.4 8 1 2 1 16/32 7.5 3000 187.5 PASS
DL.1 1 2 4 1 16/32 16 400 400 PASS

99 (K=16)

195 (K=32)
DL.2 1 2 4 1 16/32 16 400 400 PASS
DL.3 1 2 4 1 16/32 16 400 400 PASS
DL.4 1 2 4 1 16/32 16 400 400 PASS
DL.1 1 2 8 1 16/32 16 400 400 PASS

195 (K=16)

323 (K=32)
DL.2 1 2 8 1 16/32 16 400 400 PASS
DL.3 1 2 8 1 16/32 16 400 400 PASS
DL.4 1 2 8 1 16/32 16 400 400 PASS
DL.1 2 2 2 1 16/32 16 800 400 PASS

75 (K=16)

115 (K=32)
DL.2 2 2 2 1 16/32 16 800 400 PASS
DL.3 2 2 2 1 16/32 16 800 400 PASS
DL.4 2 2 2 1 16/32 16 800 400 PASS
DL.1 2 2 4 1 16/32 16 800 400 PASS

115 (K=16)

195 (K=32)
DL.2 2 2 4 1 16/32 16 800 400 PASS
DL.3 2 2 4 1 16/32 16 800 400 PASS
DL.4 2 2 4 1 16/32 16 800 400 PASS
DL.1 4 2 1 1 20/32 16 1600 400 PASS

53 (K=20)

70 (K=32)
DL.2 4 2 1 1 20/32 16 1600 400 PASS
DL.3 4 2 1 1 20/32 16 1600 400 PASS
DL.4 4 2 1 1 20/32 16 1600 400 PASS
DL.1 4 2 2 1 16/32 16 1600 400 PASS

67 (K=16)

103 (K=32)
DL.2 4 2 2 1 16/32 16 1600 400 PASS
DL.3 4 2 2 1 16/32 16 1600 400 PASS
DL.4 4 2 2 1 16/32 16 1600 400 PASS
DL.1 8 2 1 1 20/32 15 3000 375 PASS

55 (K=20)

67 (K=32)
DL.2 8 2 1 1 20/32 15 3000 375 PASS
DL.3 8 2 1 1 20/32 15 3000 375 PASS
DL.4 8 2 1 1 20/32 15 3000 375 PASS
DL.1 8 2 2 1 16/32 15 3000 375 PASS

67 (K=16)

99 (K=32)
DL.2 8 2 2 1 16/32 15 3000 375 PASS
DL.3 8 2 2 1 16/32 15 3000 375 PASS
DL.4 8 2 2 1 16/32 15 3000 375 PASS
DL.1 1 4 8 1 16/32 16 400 400 PASS

195 (K=16)

323 (K=32)
DL.2 1 4 8 1 16/32 16 400 400 PASS
DL.3 1 4 8 1 16/32 16 400 400 PASS
DL.4 1 4 8 1 16/32 16 400 400 PASS
DL.1 2 4 4 1 16/32 16 800 400 PASS

115 (K=16)

195 (K=32)
DL.2 2 4 4 1 16/32 16 800 400 PASS
DL.3 2 4 4 1 16/32 16 800 400 PASS
DL.4 2 4 4 1 16/32 16 800 400 PASS
DL.1 2 4 8 1 16/32 16 800 400 PASS

195 (K=16)

323 (K=32)
DL.2 2 4 8 1 16/32 16 800 400 PASS
DL.3 2 4 8 1 16/32 16 800 400 PASS
DL.4 2 4 8 1 16/32 16 800 400 PASS
DL.1 4 4 2 1 16/32 16 1600 400 PASS

67 (K=16)

99 (K=32)
DL.2 4 4 2 1 16/32 16 1600 400 PASS
DL.3 4 4 2 1 16/32 16 1600 400 PASS
DL.4 4 4 2 1 16/32 16 1600 400 PASS
DL.1 4 4 4 1 16/32 16 1600 400 PASS

103 (K=16)

163 (K=32)
DL.2 4 4 4 1 16/32 16 1600 400 PASS
DL.3 4 4 4 1 16/32 16 1600 400 PASS
DL.4 4 4 4 1 16/32 16 1600 400 PASS
DL.1 8 4 1 1 20/32 15 3000 375 PASS

55 (K=20)

67 (K=32)
DL.2 8 4 1 1 20/32 15 3000 375 PASS
DL.3 8 4 1 1 20/32 15 3000 375 PASS
DL.4 8 4 1 1 20/32 15 3000 375 PASS
DL.1 8 4 2 1 16/32 15 3000 375 PASS

67 (K=16)

99 (K=32)
DL.2 8 4 2 1 16/32 15 3000 375 PASS
DL.3 8 4 2 1 16/32 15 3000 375 PASS
DL.4 8 4 2 1 16/32 15 3000 375 PASS
DL.1 2 8 8 1 16/32 16 400 400 PASS

195 (K=16)

323 (K=32)
DL.2 2 8 8 1 16/32 16 400 400 PASS
DL.3 2 8 8 1 16/32 16 400 400 PASS
DL.4 2 8 8 1 16/32 16 400 400 PASS
DL.1 4 8 4 1 16/32 16 800 400 PASS

115 (K=16)

195 (K=32)
DL.2 4 8 4 1 16/32 16 800 400 PASS
DL.3 4 8 4 1 16/32 16 800 400 PASS
DL.4 4 8 4 1 16/32 16 800 400 PASS
DL.1 4 8 8 1 16/32 16 800 400 PASS

195 (K=16)

323 (K=32)
DL.2 4 8 8 1 16/32 16 800 400 PASS
DL.3 4 8 8 1 16/32 16 800 400 PASS
DL.4 4 8 8 1 16/32 16 800 400 PASS
DL.1 8 8 2 1 16/32 16 1600 400 PASS

67 (K=16)

103 (K=32)
DL.2 8 8 2 1 16/32 16 1600 400 PASS
DL.3 8 8 2 1 16/32 16 1600 400 PASS
DL.4 8 8 2 1 16/32 16 1600 400 PASS
DL.1 8 8 4 1 16/32 16 1600 400 PASS

103 (K=16)

163 (K=32)
DL.2 8 8 4 1 16/32 16 1600 400 PASS
DL.3 8 8 4 1 16/32 16 1600 400 PASS
DL.4 8 8 4 1 16/32 16 1600 400 PASS

The following figure shows the Signal Tap waveform of the clock count from the deassertion of SYNC~ to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test case). The clock count measures the first user data output latency.

Figure 6. Deterministic Latency Measurement Ramp Test Pattern Diagram
Related Information
5 Refer to Test Result Comments section for details.
Level Two Title