AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

ID 683657
Date 12/18/2017

Test Result Comments

In each test case, the JESD204B receiver IP core successfully initialize from CGS phase, ILA phase, and until user data phase.

No data integrity issue is observed by the PRBS and Ramp checker for all JESD configurations except where LMF=882, 884, and K=32. In these two configurations, momentary running disparity and 'Not in Table' errors are observed when link is running for durations longer than 15 minutes. These errors are random and only observed when Ramp data pattern is being transmitted by the converter. With PRBS-9 data pattern, no such errors are observed even when link has operated for long durations. The above mentioned configurations have been marked as PASS with comments for this reason.

In the deterministic latency measurement, consistent total latency is observed across multiple power cycles or resets.

For a few JESD configurations, in order to avoid lane de-skew error or achieve deterministic latency on FPGA, RBD offset register needs to be programmed. The modes and the corresponding values used are tabled below.

Mode (LMF) csr_rbd_offset (syncn_sysref_ctrl [10:3])
212-K32 0xC
212-K16 0x2
421-K32 0x5
422-K32 0xC
444-K16 0xC
821-K20 0x3
841-K20 0x3
882-K32 0xC
884-K16 0xC

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