AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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ID 683657
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Receiver Transport Layer

To check the data integrity of the payload data stream through the JESD204B receiver IP Core and transport layer, the ADC is configured to output PRBS-9 and Ramp test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP Core. The PRBS checker/Ramp checker in the FPGA fabric checks data integrity for one minute.

This figure shows the conceptual test setup for data integrity checking.
Figure 3. Data Integrity Check Using PRBS/Ramp Checker
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria

TL.1

 Check the transport layer mapping using Ramp test pattern.

The following signals in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid

The following signals in jesd204b_ed.sv are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The data_error signal indicates a pass or fail for the PRBS checker.
  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.

TL.2

 Check the transport layer mapping using PRBS-9 test pattern.

The following signals in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid

The following signals in jesd204b_ed.sv are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The data_error signal indicates a pass or fail for the PRBS checker.
  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.
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