AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

ID 683657
Date 12/18/2017

Hardware Setup

An Intel® Arria® 10 GX FPGA Development Kit is used with the ADI AD9208 daughter card module installed to the development board’s FMC connector.

  • The AD9208 EVM derives power from FMC pins.
  • The FPGA and ADC device clocks are supplied by external clock source card through SMA connectors on Intel® Arria® 10 FPGA kit and AD9208 EVM.
  • Both FPGA and ADC device clocks must be sourced from the same clock source card with two different frequencies, one for FPGA, and one for ADC.
  • For subclass 1, FPGA generates SYSREF for the JESD204B IP as well as the AD9208 device.
  • SYSREF is provided to ADC through SMA connector.
Figure 1. Hardware setup

The following system-level diagram shows how the different modules connect in this design.

Figure 2. System Diagram
Note: The IOPLL input reference clock is sourcing from device clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network might introduce additional jitter to the IOPLL and transceiver PLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.

In this setup, where LMF=882, the data rate of transceiver lanes is 16 Gbps. An external clock source card provides 400 MHz clock to the FPGA and 1600 MHz sampling clock to AD9208 device. A periodic SYSREF is generated by the FPGA and provided to the ADC through SMA connector.